210 	u32 hcsr, reg;  in mei_me_hw_config()  local
213 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_config()
214 	dev->hbuf_depth = (hcsr & H_CBD) >> 24;  in mei_me_hw_config()
251 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_clear()  local
253 	if (hcsr & H_CSR_IS_MASK)  in mei_me_intr_clear()
254 		mei_hcsr_write(dev, hcsr);  in mei_me_intr_clear()
263 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_enable()  local
265 	hcsr |= H_CSR_IE_MASK;  in mei_me_intr_enable()
266 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_enable()
276 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_disable()  local
278 	hcsr  &= ~H_CSR_IE_MASK;  in mei_me_intr_disable()
279 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_disable()
289 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset_release()  local
291 	hcsr |= H_IG;  in mei_me_hw_reset_release()
292 	hcsr &= ~H_RST;  in mei_me_hw_reset_release()
293 	mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset_release()
306 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_set_ready()  local
308 	hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;  in mei_me_host_set_ready()
309 	mei_hcsr_set(dev, hcsr);  in mei_me_host_set_ready()
320 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_is_ready()  local
322 	return (hcsr & H_RDY) == H_RDY;  in mei_me_host_is_ready()
390 	u32 hcsr;  in mei_hbuf_filled_slots()  local
393 	hcsr = mei_hcsr_read(dev);  in mei_hbuf_filled_slots()
395 	read_ptr = (char) ((hcsr & H_CBRP) >> 8);  in mei_hbuf_filled_slots()
396 	write_ptr = (char) ((hcsr & H_CBWP) >> 16);  in mei_hbuf_filled_slots()
463 	u32 hcsr;  in mei_me_write_message()  local
490 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_me_write_message()
491 	mei_hcsr_set(dev, hcsr);  in mei_me_write_message()
538 	u32 hcsr;  in mei_me_read_slots()  local
549 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_me_read_slots()
550 	mei_hcsr_set(dev, hcsr);  in mei_me_read_slots()
1051 	u32 hcsr;  in mei_me_hw_reset()  local
1062 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1068 	if ((hcsr & H_RST) == H_RST) {  in mei_me_hw_reset()
1069 		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);  in mei_me_hw_reset()
1070 		hcsr &= ~H_RST;  in mei_me_hw_reset()
1071 		mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset()
1072 		hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1075 	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;  in mei_me_hw_reset()
1078 		hcsr &= ~H_CSR_IE_MASK;  in mei_me_hw_reset()
1081 	mei_hcsr_write(dev, hcsr);  in mei_me_hw_reset()
1087 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
1089 	if ((hcsr & H_RST) == 0)  in mei_me_hw_reset()
1090 		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);  in mei_me_hw_reset()
1092 	if ((hcsr & H_RDY) == H_RDY)  in mei_me_hw_reset()
1093 		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);  in mei_me_hw_reset()
1118 	u32 hcsr;  in mei_me_irq_quick_handler()  local
1120 	hcsr = mei_hcsr_read(dev);  in mei_me_irq_quick_handler()
1121 	if (!(hcsr & H_CSR_IS_MASK))  in mei_me_irq_quick_handler()
1124 	hw->intr_source = hcsr & H_CSR_IS_MASK;  in mei_me_irq_quick_handler()
1128 	mei_hcsr_write(dev, hcsr);  in mei_me_irq_quick_handler()