69 static void enable_dbi_access(struct pcie_app_reg __iomem *app_reg)  in enable_dbi_access()  argument
72 	writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID),  in enable_dbi_access()
73 			&app_reg->slv_armisc);  in enable_dbi_access()
74 	writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID),  in enable_dbi_access()
75 			&app_reg->slv_awmisc);  in enable_dbi_access()
79 static void disable_dbi_access(struct pcie_app_reg __iomem *app_reg)  in disable_dbi_access()  argument
82 	writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),  in disable_dbi_access()
83 			&app_reg->slv_armisc);  in disable_dbi_access()
84 	writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),  in disable_dbi_access()
85 			&app_reg->slv_awmisc);  in disable_dbi_access()
92 	struct pcie_app_reg __iomem *app_reg = config->va_app_base;  in spear_dbi_read_reg()  local
96 	enable_dbi_access(app_reg);  in spear_dbi_read_reg()
108 	disable_dbi_access(app_reg);  in spear_dbi_read_reg()
114 	struct pcie_app_reg __iomem *app_reg = config->va_app_base;  in spear_dbi_write_reg()  local
118 	enable_dbi_access(app_reg);  in spear_dbi_write_reg()
130 	disable_dbi_access(app_reg);  in spear_dbi_write_reg()
233 	struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;  in pcie_gadget_link_show()  local
235 	if (readl(&app_reg->app_status_1) & ((u32)1 << XMLH_LINK_UP_ID))  in pcie_gadget_link_show()
244 	struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;  in pcie_gadget_link_store()  local
247 		writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID),  in pcie_gadget_link_store()
248 			&app_reg->app_ctrl_0);  in pcie_gadget_link_store()
250 		writel(readl(&app_reg->app_ctrl_0)  in pcie_gadget_link_store()
252 				&app_reg->app_ctrl_0);  in pcie_gadget_link_store()
297 	struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;  in pcie_gadget_no_of_msi_show()
301 	if ((readl(&app_reg->msg_status) & (1 << CFG_MSI_EN_ID))  in pcie_gadget_no_of_msi_show()
336 	struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;  in pcie_gadget_inta_store()  local
345 		writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID),  in pcie_gadget_inta_store()
346 				&app_reg->app_ctrl_0);  in pcie_gadget_inta_store()
348 		writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID),  in pcie_gadget_inta_store()
349 				&app_reg->app_ctrl_0);  in pcie_gadget_inta_store()
358 	struct pcie_app_reg __iomem *app_reg = config->va_app_base;  in pcie_gadget_send_msi_store()
373 	ven_msi = readl(&app_reg->ven_msi_1);  in pcie_gadget_send_msi_store()
383 	writel(ven_msi, &app_reg->ven_msi_1);  in pcie_gadget_send_msi_store()
386 	writel(ven_msi, &app_reg->ven_msi_1);  in pcie_gadget_send_msi_store()
487 	struct pcie_app_reg __iomem *app_reg = to_target(item)->va_app_base;  in pcie_gadget_bar0_address_show()  local
489 	u32 address = readl(&app_reg->pim0_mem_addr_start);  in pcie_gadget_bar0_address_show()
498 	struct pcie_app_reg __iomem *app_reg = config->va_app_base;  in pcie_gadget_bar0_address_store()
513 	writel(address, &app_reg->pim0_mem_addr_start);  in pcie_gadget_bar0_address_store()
608 	struct pcie_app_reg __iomem *app_reg = config->va_app_base;  in spear13xx_pcie_device_init()  local
612 	writel(config->base, &app_reg->in0_mem_addr_start);  in spear13xx_pcie_device_init()
613 	writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE,  in spear13xx_pcie_device_init()
614 			&app_reg->in0_mem_addr_limit);  in spear13xx_pcie_device_init()
615 	writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start);  in spear13xx_pcie_device_init()
616 	writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE,  in spear13xx_pcie_device_init()
617 			&app_reg->in1_mem_addr_limit);  in spear13xx_pcie_device_init()
618 	writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start);  in spear13xx_pcie_device_init()
619 	writel(app_reg->in_io_addr_start + IN_IO_SIZE,  in spear13xx_pcie_device_init()
620 			&app_reg->in_io_addr_limit);  in spear13xx_pcie_device_init()
621 	writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start);  in spear13xx_pcie_device_init()
622 	writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE,  in spear13xx_pcie_device_init()
623 			&app_reg->in_cfg0_addr_limit);  in spear13xx_pcie_device_init()
624 	writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start);  in spear13xx_pcie_device_init()
625 	writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE,  in spear13xx_pcie_device_init()
626 			&app_reg->in_cfg1_addr_limit);  in spear13xx_pcie_device_init()
627 	writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start);  in spear13xx_pcie_device_init()
628 	writel(app_reg->in_msg_addr_start + IN_MSG_SIZE,  in spear13xx_pcie_device_init()
629 			&app_reg->in_msg_addr_limit);  in spear13xx_pcie_device_init()
631 	writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start);  in spear13xx_pcie_device_init()
632 	writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start);  in spear13xx_pcie_device_init()
633 	writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start);  in spear13xx_pcie_device_init()
644 	writel(SPEAR13XX_SYSRAM1_BASE, &app_reg->pim0_mem_addr_start);  in spear13xx_pcie_device_init()
645 	writel(0, &app_reg->pim1_mem_addr_start);  in spear13xx_pcie_device_init()
646 	writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit);  in spear13xx_pcie_device_init()
648 	writel(0x0, &app_reg->pim_io_addr_start);  in spear13xx_pcie_device_init()
649 	writel(0x0, &app_reg->pim_io_addr_start);  in spear13xx_pcie_device_init()
650 	writel(0x0, &app_reg->pim_rom_addr_start);  in spear13xx_pcie_device_init()
654 			&app_reg->app_ctrl_0);  in spear13xx_pcie_device_init()
656 	writel(0, &app_reg->int_mask);  in spear13xx_pcie_device_init()