Lines Matching refs:denali
104 static void clear_interrupts(struct denali_nand_info *denali);
105 static uint32_t wait_for_irq(struct denali_nand_info *denali,
107 static void denali_irq_enable(struct denali_nand_info *denali,
109 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
117 static void index_addr(struct denali_nand_info *denali, in index_addr() argument
120 iowrite32(address, denali->flash_mem); in index_addr()
121 iowrite32(data, denali->flash_mem + 0x10); in index_addr()
125 static void index_addr_read_data(struct denali_nand_info *denali, in index_addr_read_data() argument
128 iowrite32(address, denali->flash_mem); in index_addr_read_data()
129 *pdata = ioread32(denali->flash_mem + 0x10); in index_addr_read_data()
136 static void reset_buf(struct denali_nand_info *denali) in reset_buf() argument
138 denali->buf.head = denali->buf.tail = 0; in reset_buf()
141 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) in write_byte_to_buf() argument
143 denali->buf.buf[denali->buf.tail++] = byte; in write_byte_to_buf()
147 static void read_status(struct denali_nand_info *denali) in read_status() argument
152 reset_buf(denali); in read_status()
154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT); in read_status()
156 write_byte_to_buf(denali, NAND_STATUS_WP); in read_status()
158 write_byte_to_buf(denali, 0); in read_status()
162 static void reset_bank(struct denali_nand_info *denali) in reset_bank() argument
167 clear_interrupts(denali); in reset_bank()
169 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); in reset_bank()
171 irq_status = wait_for_irq(denali, irq_mask); in reset_bank()
174 dev_err(denali->dev, "reset bank failed.\n"); in reset_bank()
178 static uint16_t denali_nand_reset(struct denali_nand_info *denali) in denali_nand_reset() argument
182 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", in denali_nand_reset()
185 for (i = 0; i < denali->max_banks; i++) in denali_nand_reset()
187 denali->flash_reg + INTR_STATUS(i)); in denali_nand_reset()
189 for (i = 0; i < denali->max_banks; i++) { in denali_nand_reset()
190 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); in denali_nand_reset()
191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & in denali_nand_reset()
194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) & in denali_nand_reset()
196 dev_dbg(denali->dev, in denali_nand_reset()
200 for (i = 0; i < denali->max_banks; i++) in denali_nand_reset()
202 denali->flash_reg + INTR_STATUS(i)); in denali_nand_reset()
212 static void nand_onfi_timing_set(struct denali_nand_info *denali, in nand_onfi_timing_set() argument
234 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", in nand_onfi_timing_set()
270 dev_warn(denali->dev, "%s, Line %d: Warning!\n", in nand_onfi_timing_set()
292 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && in nand_onfi_timing_set()
293 ioread32(denali->flash_reg + DEVICE_ID) == 0x88) in nand_onfi_timing_set()
296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); in nand_onfi_timing_set()
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE); in nand_onfi_timing_set()
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE); in nand_onfi_timing_set()
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE); in nand_onfi_timing_set()
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); in nand_onfi_timing_set()
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); in nand_onfi_timing_set()
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); in nand_onfi_timing_set()
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); in nand_onfi_timing_set()
307 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) in get_onfi_nand_para() argument
315 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & in get_onfi_nand_para()
320 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & in get_onfi_nand_para()
325 nand_onfi_timing_set(denali, i); in get_onfi_nand_para()
337 static void get_samsung_nand_para(struct denali_nand_info *denali, in get_samsung_nand_para() argument
342 iowrite32(5, denali->flash_reg + ACC_CLKS); in get_samsung_nand_para()
343 iowrite32(20, denali->flash_reg + RE_2_WE); in get_samsung_nand_para()
344 iowrite32(12, denali->flash_reg + WE_2_RE); in get_samsung_nand_para()
345 iowrite32(14, denali->flash_reg + ADDR_2_DATA); in get_samsung_nand_para()
346 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); in get_samsung_nand_para()
347 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); in get_samsung_nand_para()
348 iowrite32(2, denali->flash_reg + CS_SETUP_CNT); in get_samsung_nand_para()
352 static void get_toshiba_nand_para(struct denali_nand_info *denali) in get_toshiba_nand_para() argument
360 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && in get_toshiba_nand_para()
361 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { in get_toshiba_nand_para()
362 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); in get_toshiba_nand_para()
363 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * in get_toshiba_nand_para()
364 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); in get_toshiba_nand_para()
366 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); in get_toshiba_nand_para()
368 iowrite32(15, denali->flash_reg + ECC_CORRECTION); in get_toshiba_nand_para()
370 iowrite32(8, denali->flash_reg + ECC_CORRECTION); in get_toshiba_nand_para()
375 static void get_hynix_nand_para(struct denali_nand_info *denali, in get_hynix_nand_para() argument
383 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); in get_hynix_nand_para()
384 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); in get_hynix_nand_para()
385 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); in get_hynix_nand_para()
387 ioread32(denali->flash_reg + DEVICES_CONNECTED); in get_hynix_nand_para()
389 ioread32(denali->flash_reg + DEVICES_CONNECTED); in get_hynix_nand_para()
391 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); in get_hynix_nand_para()
393 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); in get_hynix_nand_para()
394 iowrite32(0, denali->flash_reg + DEVICE_WIDTH); in get_hynix_nand_para()
396 iowrite32(15, denali->flash_reg + ECC_CORRECTION); in get_hynix_nand_para()
398 iowrite32(8, denali->flash_reg + ECC_CORRECTION); in get_hynix_nand_para()
402 dev_warn(denali->dev, in get_hynix_nand_para()
413 static void find_valid_banks(struct denali_nand_info *denali) in find_valid_banks() argument
415 uint32_t id[denali->max_banks]; in find_valid_banks()
418 denali->total_used_banks = 1; in find_valid_banks()
419 for (i = 0; i < denali->max_banks; i++) { in find_valid_banks()
420 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); in find_valid_banks()
421 index_addr(denali, MODE_11 | (i << 24) | 1, 0); in find_valid_banks()
422 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); in find_valid_banks()
424 dev_dbg(denali->dev, in find_valid_banks()
432 denali->total_used_banks++; in find_valid_banks()
438 if (denali->platform == INTEL_CE4100) { in find_valid_banks()
444 if (denali->total_used_banks != 1) { in find_valid_banks()
445 dev_err(denali->dev, in find_valid_banks()
450 dev_dbg(denali->dev, in find_valid_banks()
451 "denali->total_used_banks: %d\n", denali->total_used_banks); in find_valid_banks()
458 static void detect_max_banks(struct denali_nand_info *denali) in detect_max_banks() argument
460 uint32_t features = ioread32(denali->flash_reg + FEATURES); in detect_max_banks()
466 ioread32(denali->flash_reg + REVISION)); in detect_max_banks()
469 denali->max_banks = 2 << (features & FEATURES__N_BANKS); in detect_max_banks()
471 denali->max_banks = 1 << (features & FEATURES__N_BANKS); in detect_max_banks()
474 static void detect_partition_feature(struct denali_nand_info *denali) in detect_partition_feature() argument
483 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { in detect_partition_feature()
484 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & in detect_partition_feature()
486 denali->fwblks = in detect_partition_feature()
487 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & in detect_partition_feature()
489 denali->blksperchip) in detect_partition_feature()
491 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & in detect_partition_feature()
494 denali->fwblks = SPECTRA_START_BLOCK; in detect_partition_feature()
497 denali->fwblks = SPECTRA_START_BLOCK; in detect_partition_feature()
501 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) in denali_nand_timing_set() argument
508 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", in denali_nand_timing_set()
516 addr = MODE_11 | BANK(denali->flash_bank); in denali_nand_timing_set()
517 index_addr(denali, addr | 0, 0x90); in denali_nand_timing_set()
518 index_addr(denali, addr | 1, 0); in denali_nand_timing_set()
520 index_addr_read_data(denali, addr | 2, &id_bytes[i]); in denali_nand_timing_set()
524 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & in denali_nand_timing_set()
526 if (FAIL == get_onfi_nand_para(denali)) in denali_nand_timing_set()
529 get_samsung_nand_para(denali, device_id); in denali_nand_timing_set()
531 get_toshiba_nand_para(denali); in denali_nand_timing_set()
533 get_hynix_nand_para(denali, device_id); in denali_nand_timing_set()
536 dev_info(denali->dev, in denali_nand_timing_set()
541 ioread32(denali->flash_reg + ACC_CLKS), in denali_nand_timing_set()
542 ioread32(denali->flash_reg + RE_2_WE), in denali_nand_timing_set()
543 ioread32(denali->flash_reg + RE_2_RE), in denali_nand_timing_set()
544 ioread32(denali->flash_reg + WE_2_RE), in denali_nand_timing_set()
545 ioread32(denali->flash_reg + ADDR_2_DATA), in denali_nand_timing_set()
546 ioread32(denali->flash_reg + RDWR_EN_LO_CNT), in denali_nand_timing_set()
547 ioread32(denali->flash_reg + RDWR_EN_HI_CNT), in denali_nand_timing_set()
548 ioread32(denali->flash_reg + CS_SETUP_CNT)); in denali_nand_timing_set()
550 find_valid_banks(denali); in denali_nand_timing_set()
552 detect_partition_feature(denali); in denali_nand_timing_set()
559 nand_onfi_timing_set(denali, onfi_timing_mode); in denali_nand_timing_set()
564 static void denali_set_intr_modes(struct denali_nand_info *denali, in denali_set_intr_modes() argument
567 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", in denali_set_intr_modes()
571 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); in denali_set_intr_modes()
573 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); in denali_set_intr_modes()
585 static void denali_irq_init(struct denali_nand_info *denali) in denali_irq_init() argument
591 denali_set_intr_modes(denali, false); in denali_irq_init()
596 for (i = 0; i < denali->max_banks; ++i) in denali_irq_init()
597 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); in denali_irq_init()
599 denali_irq_enable(denali, int_mask); in denali_irq_init()
602 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) in denali_irq_cleanup() argument
604 denali_set_intr_modes(denali, false); in denali_irq_cleanup()
605 free_irq(irqnum, denali); in denali_irq_cleanup()
608 static void denali_irq_enable(struct denali_nand_info *denali, in denali_irq_enable() argument
613 for (i = 0; i < denali->max_banks; ++i) in denali_irq_enable()
614 iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); in denali_irq_enable()
621 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) in denali_irq_detected() argument
623 return read_interrupt_status(denali) & DENALI_IRQ_ALL; in denali_irq_detected()
627 static inline void clear_interrupt(struct denali_nand_info *denali, in clear_interrupt() argument
632 intr_status_reg = INTR_STATUS(denali->flash_bank); in clear_interrupt()
634 iowrite32(irq_mask, denali->flash_reg + intr_status_reg); in clear_interrupt()
637 static void clear_interrupts(struct denali_nand_info *denali) in clear_interrupts() argument
641 spin_lock_irq(&denali->irq_lock); in clear_interrupts()
643 status = read_interrupt_status(denali); in clear_interrupts()
644 clear_interrupt(denali, status); in clear_interrupts()
646 denali->irq_status = 0x0; in clear_interrupts()
647 spin_unlock_irq(&denali->irq_lock); in clear_interrupts()
650 static uint32_t read_interrupt_status(struct denali_nand_info *denali) in read_interrupt_status() argument
654 intr_status_reg = INTR_STATUS(denali->flash_bank); in read_interrupt_status()
656 return ioread32(denali->flash_reg + intr_status_reg); in read_interrupt_status()
665 struct denali_nand_info *denali = dev_id; in denali_isr() local
669 spin_lock(&denali->irq_lock); in denali_isr()
672 if (is_flash_bank_valid(denali->flash_bank)) { in denali_isr()
677 irq_status = denali_irq_detected(denali); in denali_isr()
681 clear_interrupt(denali, irq_status); in denali_isr()
686 denali->irq_status |= irq_status; in denali_isr()
688 complete(&denali->complete); in denali_isr()
693 spin_unlock(&denali->irq_lock); in denali_isr()
698 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) in wait_for_irq() argument
706 wait_for_completion_timeout(&denali->complete, timeout); in wait_for_irq()
707 spin_lock_irq(&denali->irq_lock); in wait_for_irq()
708 intr_status = denali->irq_status; in wait_for_irq()
711 denali->irq_status &= ~irq_mask; in wait_for_irq()
712 spin_unlock_irq(&denali->irq_lock); in wait_for_irq()
721 spin_unlock_irq(&denali->irq_lock); in wait_for_irq()
738 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, in setup_ecc_for_xfer() argument
748 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); in setup_ecc_for_xfer()
749 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); in setup_ecc_for_xfer()
756 static int denali_send_pipeline_cmd(struct denali_nand_info *denali, in denali_send_pipeline_cmd() argument
771 setup_ecc_for_xfer(denali, ecc_en, transfer_spare); in denali_send_pipeline_cmd()
773 clear_interrupts(denali); in denali_send_pipeline_cmd()
775 addr = BANK(denali->flash_bank) | denali->page; in denali_send_pipeline_cmd()
779 iowrite32(cmd, denali->flash_mem); in denali_send_pipeline_cmd()
783 index_addr(denali, cmd, access_type); in denali_send_pipeline_cmd()
786 iowrite32(cmd, denali->flash_mem); in denali_send_pipeline_cmd()
790 index_addr(denali, cmd, access_type); in denali_send_pipeline_cmd()
799 iowrite32(cmd, denali->flash_mem); in denali_send_pipeline_cmd()
801 index_addr(denali, cmd, in denali_send_pipeline_cmd()
809 irq_status = wait_for_irq(denali, irq_mask); in denali_send_pipeline_cmd()
812 dev_err(denali->dev, in denali_send_pipeline_cmd()
814 cmd, denali->page, addr); in denali_send_pipeline_cmd()
818 iowrite32(cmd, denali->flash_mem); in denali_send_pipeline_cmd()
826 static int write_data_to_flash_mem(struct denali_nand_info *denali, in write_data_to_flash_mem() argument
841 iowrite32(*buf32++, denali->flash_mem + 0x10); in write_data_to_flash_mem()
846 static int read_data_from_flash_mem(struct denali_nand_info *denali, in read_data_from_flash_mem() argument
863 *buf32++ = ioread32(denali->flash_mem + 0x10); in read_data_from_flash_mem()
870 struct denali_nand_info *denali = mtd_to_denali(mtd); in write_oob_data() local
876 denali->page = page; in write_oob_data()
878 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, in write_oob_data()
880 write_data_to_flash_mem(denali, buf, mtd->oobsize); in write_oob_data()
883 irq_status = wait_for_irq(denali, irq_mask); in write_oob_data()
886 dev_err(denali->dev, "OOB write failed\n"); in write_oob_data()
890 dev_err(denali->dev, "unable to send pipeline command\n"); in write_oob_data()
899 struct denali_nand_info *denali = mtd_to_denali(mtd); in read_oob_data() local
903 denali->page = page; in read_oob_data()
905 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, in read_oob_data()
907 read_data_from_flash_mem(denali, buf, mtd->oobsize); in read_oob_data()
914 irq_status = wait_for_irq(denali, irq_mask); in read_oob_data()
917 dev_err(denali->dev, "page on OOB timeout %d\n", in read_oob_data()
918 denali->page); in read_oob_data()
927 addr = BANK(denali->flash_bank) | denali->page; in read_oob_data()
929 index_addr(denali, cmd, MAIN_ACCESS); in read_oob_data()
955 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, in handle_ecc() argument
965 denali_set_intr_modes(denali, false); in handle_ecc()
968 err_address = ioread32(denali->flash_reg + in handle_ecc()
973 err_correction_info = ioread32(denali->flash_reg + in handle_ecc()
994 denali->devnum + in handle_ecc()
998 denali->mtd.ecc_stats.corrected++; in handle_ecc()
1015 while (!(read_interrupt_status(denali) & in handle_ecc()
1018 clear_interrupts(denali); in handle_ecc()
1019 denali_set_intr_modes(denali, true); in handle_ecc()
1026 static void denali_enable_dma(struct denali_nand_info *denali, bool en) in denali_enable_dma() argument
1028 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); in denali_enable_dma()
1029 ioread32(denali->flash_reg + DMA_ENABLE); in denali_enable_dma()
1033 static void denali_setup_dma(struct denali_nand_info *denali, int op) in denali_setup_dma() argument
1037 uint32_t addr = denali->buf.dma_buf; in denali_setup_dma()
1039 mode = MODE_10 | BANK(denali->flash_bank); in denali_setup_dma()
1044 index_addr(denali, mode | denali->page, 0x2000 | op | page_count); in denali_setup_dma()
1047 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); in denali_setup_dma()
1050 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); in denali_setup_dma()
1053 index_addr(denali, mode | 0x14000, 0x2400); in denali_setup_dma()
1063 struct denali_nand_info *denali = mtd_to_denali(mtd); in write_page() local
1064 dma_addr_t addr = denali->buf.dma_buf; in write_page()
1065 size_t size = denali->mtd.writesize + denali->mtd.oobsize; in write_page()
1075 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); in write_page()
1078 memcpy(denali->buf.buf, buf, mtd->writesize); in write_page()
1082 memcpy(denali->buf.buf + mtd->writesize, in write_page()
1087 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); in write_page()
1089 clear_interrupts(denali); in write_page()
1090 denali_enable_dma(denali, true); in write_page()
1092 denali_setup_dma(denali, DENALI_WRITE); in write_page()
1095 irq_status = wait_for_irq(denali, irq_mask); in write_page()
1098 dev_err(denali->dev, "timeout on write_page (type = %d)\n", in write_page()
1100 denali->status = NAND_STATUS_FAIL; in write_page()
1103 denali_enable_dma(denali, false); in write_page()
1104 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); in write_page()
1160 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_read_page() local
1162 dma_addr_t addr = denali->buf.dma_buf; in denali_read_page()
1163 size_t size = denali->mtd.writesize + denali->mtd.oobsize; in denali_read_page()
1170 if (page != denali->page) { in denali_read_page()
1171 dev_err(denali->dev, in denali_read_page()
1173 __func__, page, denali->page); in denali_read_page()
1177 setup_ecc_for_xfer(denali, true, false); in denali_read_page()
1179 denali_enable_dma(denali, true); in denali_read_page()
1180 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); in denali_read_page()
1182 clear_interrupts(denali); in denali_read_page()
1183 denali_setup_dma(denali, DENALI_READ); in denali_read_page()
1186 irq_status = wait_for_irq(denali, irq_mask); in denali_read_page()
1188 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); in denali_read_page()
1190 memcpy(buf, denali->buf.buf, mtd->writesize); in denali_read_page()
1192 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); in denali_read_page()
1193 denali_enable_dma(denali, false); in denali_read_page()
1196 read_oob_data(&denali->mtd, chip->oob_poi, denali->page); in denali_read_page()
1200 if (!is_erased(buf, denali->mtd.writesize)) in denali_read_page()
1201 denali->mtd.ecc_stats.failed++; in denali_read_page()
1202 if (!is_erased(buf, denali->mtd.oobsize)) in denali_read_page()
1203 denali->mtd.ecc_stats.failed++; in denali_read_page()
1212 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_read_page_raw() local
1213 dma_addr_t addr = denali->buf.dma_buf; in denali_read_page_raw()
1214 size_t size = denali->mtd.writesize + denali->mtd.oobsize; in denali_read_page_raw()
1217 if (page != denali->page) { in denali_read_page_raw()
1218 dev_err(denali->dev, in denali_read_page_raw()
1220 __func__, page, denali->page); in denali_read_page_raw()
1224 setup_ecc_for_xfer(denali, false, true); in denali_read_page_raw()
1225 denali_enable_dma(denali, true); in denali_read_page_raw()
1227 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); in denali_read_page_raw()
1229 clear_interrupts(denali); in denali_read_page_raw()
1230 denali_setup_dma(denali, DENALI_READ); in denali_read_page_raw()
1233 wait_for_irq(denali, irq_mask); in denali_read_page_raw()
1235 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); in denali_read_page_raw()
1237 denali_enable_dma(denali, false); in denali_read_page_raw()
1239 memcpy(buf, denali->buf.buf, mtd->writesize); in denali_read_page_raw()
1240 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); in denali_read_page_raw()
1247 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_read_byte() local
1250 if (denali->buf.head < denali->buf.tail) in denali_read_byte()
1251 result = denali->buf.buf[denali->buf.head++]; in denali_read_byte()
1258 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_select_chip() local
1260 spin_lock_irq(&denali->irq_lock); in denali_select_chip()
1261 denali->flash_bank = chip; in denali_select_chip()
1262 spin_unlock_irq(&denali->irq_lock); in denali_select_chip()
1267 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_waitfunc() local
1268 int status = denali->status; in denali_waitfunc()
1270 denali->status = 0; in denali_waitfunc()
1277 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_erase() local
1281 clear_interrupts(denali); in denali_erase()
1284 cmd = MODE_10 | BANK(denali->flash_bank) | page; in denali_erase()
1285 index_addr(denali, cmd, 0x1); in denali_erase()
1288 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | in denali_erase()
1297 struct denali_nand_info *denali = mtd_to_denali(mtd); in denali_cmdfunc() local
1305 read_status(denali); in denali_cmdfunc()
1309 reset_buf(denali); in denali_cmdfunc()
1315 addr = MODE_11 | BANK(denali->flash_bank); in denali_cmdfunc()
1316 index_addr(denali, addr | 0, 0x90); in denali_cmdfunc()
1317 index_addr(denali, addr | 1, col); in denali_cmdfunc()
1319 index_addr_read_data(denali, addr | 2, &id); in denali_cmdfunc()
1320 write_byte_to_buf(denali, id); in denali_cmdfunc()
1325 denali->page = page; in denali_cmdfunc()
1328 reset_bank(denali); in denali_cmdfunc()
1341 static void denali_hw_init(struct denali_nand_info *denali) in denali_hw_init() argument
1349 denali->bbtskipbytes = ioread32(denali->flash_reg + in denali_hw_init()
1351 detect_max_banks(denali); in denali_hw_init()
1352 denali_nand_reset(denali); in denali_hw_init()
1353 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); in denali_hw_init()
1355 denali->flash_reg + CHIP_ENABLE_DONT_CARE); in denali_hw_init()
1357 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); in denali_hw_init()
1360 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); in denali_hw_init()
1361 iowrite32(1, denali->flash_reg + ECC_ENABLE); in denali_hw_init()
1362 denali_nand_timing_set(denali); in denali_hw_init()
1363 denali_irq_init(denali); in denali_hw_init()
1405 static void denali_drv_init(struct denali_nand_info *denali) in denali_drv_init() argument
1407 denali->idx = 0; in denali_drv_init()
1414 init_completion(&denali->complete); in denali_drv_init()
1420 spin_lock_init(&denali->irq_lock); in denali_drv_init()
1423 denali->flash_bank = CHIP_SELECT_INVALID; in denali_drv_init()
1426 denali->irq_status = 0; in denali_drv_init()
1429 int denali_init(struct denali_nand_info *denali) in denali_init() argument
1433 if (denali->platform == INTEL_CE4100) { in denali_init()
1445 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, in denali_init()
1447 if (!denali->buf.buf) in denali_init()
1450 denali->mtd.dev.parent = denali->dev; in denali_init()
1451 denali_hw_init(denali); in denali_init()
1452 denali_drv_init(denali); in denali_init()
1458 if (request_irq(denali->irq, denali_isr, IRQF_SHARED, in denali_init()
1459 DENALI_NAND_NAME, denali)) { in denali_init()
1465 denali_set_intr_modes(denali, true); in denali_init()
1466 denali->mtd.name = "denali-nand"; in denali_init()
1467 denali->mtd.priv = &denali->nand; in denali_init()
1470 denali->nand.select_chip = denali_select_chip; in denali_init()
1471 denali->nand.cmdfunc = denali_cmdfunc; in denali_init()
1472 denali->nand.read_byte = denali_read_byte; in denali_init()
1473 denali->nand.waitfunc = denali_waitfunc; in denali_init()
1480 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { in denali_init()
1486 devm_kfree(denali->dev, denali->buf.buf); in denali_init()
1487 denali->buf.buf = devm_kzalloc(denali->dev, in denali_init()
1488 denali->mtd.writesize + denali->mtd.oobsize, in denali_init()
1490 if (!denali->buf.buf) { in denali_init()
1496 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); in denali_init()
1502 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, in denali_init()
1503 denali->mtd.writesize + denali->mtd.oobsize, in denali_init()
1505 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { in denali_init()
1506 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); in denali_init()
1516 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); in denali_init()
1517 denali->nand.chipsize <<= (denali->devnum - 1); in denali_init()
1518 denali->nand.page_shift += (denali->devnum - 1); in denali_init()
1519 denali->nand.pagemask = (denali->nand.chipsize >> in denali_init()
1520 denali->nand.page_shift) - 1; in denali_init()
1521 denali->nand.bbt_erase_shift += (denali->devnum - 1); in denali_init()
1522 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; in denali_init()
1523 denali->nand.chip_shift += (denali->devnum - 1); in denali_init()
1524 denali->mtd.writesize <<= (denali->devnum - 1); in denali_init()
1525 denali->mtd.oobsize <<= (denali->devnum - 1); in denali_init()
1526 denali->mtd.erasesize <<= (denali->devnum - 1); in denali_init()
1527 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; in denali_init()
1528 denali->bbtskipbytes *= denali->devnum; in denali_init()
1537 denali->nand.bbt_td = &bbt_main_descr; in denali_init()
1538 denali->nand.bbt_md = &bbt_mirror_descr; in denali_init()
1541 denali->nand.bbt_options |= NAND_BBT_USE_FLASH; in denali_init()
1542 denali->nand.options |= NAND_SKIP_BBTSCAN; in denali_init()
1543 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; in denali_init()
1546 denali->nand.options |= NAND_NO_SUBPAGE_WRITE; in denali_init()
1553 if (!nand_is_slc(&denali->nand) && in denali_init()
1554 (denali->mtd.oobsize > (denali->bbtskipbytes + in denali_init()
1555 ECC_15BITS * (denali->mtd.writesize / in denali_init()
1558 denali->nand.ecc.strength = 15; in denali_init()
1559 denali->nand.ecc.layout = &nand_15bit_oob; in denali_init()
1560 denali->nand.ecc.bytes = ECC_15BITS; in denali_init()
1561 iowrite32(15, denali->flash_reg + ECC_CORRECTION); in denali_init()
1562 } else if (denali->mtd.oobsize < (denali->bbtskipbytes + in denali_init()
1563 ECC_8BITS * (denali->mtd.writesize / in denali_init()
1568 denali->nand.ecc.strength = 8; in denali_init()
1569 denali->nand.ecc.layout = &nand_8bit_oob; in denali_init()
1570 denali->nand.ecc.bytes = ECC_8BITS; in denali_init()
1571 iowrite32(8, denali->flash_reg + ECC_CORRECTION); in denali_init()
1574 denali->nand.ecc.bytes *= denali->devnum; in denali_init()
1575 denali->nand.ecc.strength *= denali->devnum; in denali_init()
1576 denali->nand.ecc.layout->eccbytes *= in denali_init()
1577 denali->mtd.writesize / ECC_SECTOR_SIZE; in denali_init()
1578 denali->nand.ecc.layout->oobfree[0].offset = in denali_init()
1579 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; in denali_init()
1580 denali->nand.ecc.layout->oobfree[0].length = in denali_init()
1581 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - in denali_init()
1582 denali->bbtskipbytes; in denali_init()
1589 denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; in denali_init()
1590 denali->blksperchip = denali->totalblks / denali->nand.numchips; in denali_init()
1593 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; in denali_init()
1594 denali->nand.ecc.read_page = denali_read_page; in denali_init()
1595 denali->nand.ecc.read_page_raw = denali_read_page_raw; in denali_init()
1596 denali->nand.ecc.write_page = denali_write_page; in denali_init()
1597 denali->nand.ecc.write_page_raw = denali_write_page_raw; in denali_init()
1598 denali->nand.ecc.read_oob = denali_read_oob; in denali_init()
1599 denali->nand.ecc.write_oob = denali_write_oob; in denali_init()
1600 denali->nand.erase = denali_erase; in denali_init()
1602 if (nand_scan_tail(&denali->mtd)) { in denali_init()
1607 ret = mtd_device_register(&denali->mtd, NULL, 0); in denali_init()
1609 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", in denali_init()
1616 denali_irq_cleanup(denali->irq, denali); in denali_init()
1623 void denali_remove(struct denali_nand_info *denali) in denali_remove() argument
1625 denali_irq_cleanup(denali->irq, denali); in denali_remove()
1626 dma_unmap_single(denali->dev, denali->buf.dma_buf, in denali_remove()
1627 denali->mtd.writesize + denali->mtd.oobsize, in denali_remove()