Lines Matching defs:pxa3xx_nand_info
187 struct pxa3xx_nand_info { struct
188 struct nand_hw_control controller;
189 struct platform_device *pdev;
191 struct clk *clk;
192 void __iomem *mmio_base;
193 unsigned long mmio_phys;
194 struct completion cmd_complete, dev_ready;
196 unsigned int buf_start;
197 unsigned int buf_count;
198 unsigned int buf_size;
199 unsigned int data_buff_pos;
200 unsigned int oob_buff_pos;
203 struct scatterlist sg;
204 enum dma_data_direction dma_dir;
205 struct dma_chan *dma_chan;
206 dma_cookie_t dma_cookie;
207 int drcmr_dat;
208 int drcmr_cmd;
210 unsigned char *data_buff;
211 unsigned char *oob_buff;
212 dma_addr_t data_buff_phys;
213 int data_dma_ch;
215 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
216 unsigned int state;
222 enum pxa3xx_nand_variant variant;
224 int cs;
225 int use_ecc; /* use HW ECC ? */
226 int ecc_bch; /* using BCH ECC? */
227 int use_dma; /* use DMA ? */
228 int use_spare; /* use spare ? */
229 int need_wait;
231 unsigned int data_size; /* data to be read from FIFO */
232 unsigned int chunk_size; /* split commands chunk size */
233 unsigned int oob_size;
234 unsigned int spare_size;
235 unsigned int ecc_size;
236 unsigned int ecc_err_cnt;
237 unsigned int max_bitflips;
238 int retcode;
241 uint32_t reg_ndcr;
242 uint32_t ndtr0cs0;
243 uint32_t ndtr1cs0;
246 uint32_t ndcb0;
247 uint32_t ndcb1;
248 uint32_t ndcb2;
249 uint32_t ndcb3;