Lines Matching refs:TXX9_NDFMCR
27 #define TXX9_NDFMCR 0x04 macro
118 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_write_buf()
120 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); in txx9ndfmc_write_buf()
123 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); in txx9ndfmc_write_buf()
144 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_cmd_ctrl()
155 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); in txx9ndfmc_cmd_ctrl()
180 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_calculate_ecc()
183 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); in txx9ndfmc_calculate_ecc()
184 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); in txx9ndfmc_calculate_ecc()
191 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); in txx9ndfmc_calculate_ecc()
218 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_enable_hwecc()
221 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); in txx9ndfmc_enable_hwecc()
222 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); in txx9ndfmc_enable_hwecc()
223 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); in txx9ndfmc_enable_hwecc()
252 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR); in txx9ndfmc_initialize()