Lines Matching refs:q
282 static inline int needs_swap_endian(struct fsl_qspi *q) in needs_swap_endian() argument
284 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian()
287 static inline int needs_4x_clock(struct fsl_qspi *q) in needs_4x_clock() argument
289 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock()
292 static inline int needs_fill_txfifo(struct fsl_qspi *q) in needs_fill_txfifo() argument
294 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890; in needs_fill_txfifo()
297 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) in needs_wakeup_wait_mode() argument
299 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618; in needs_wakeup_wait_mode()
306 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) in fsl_qspi_endian_xchg() argument
308 return needs_swap_endian(q) ? __swab32(a) : a; in fsl_qspi_endian_xchg()
311 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q) in fsl_qspi_unlock_lut() argument
313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_unlock_lut()
314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_unlock_lut()
317 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q) in fsl_qspi_lock_lut() argument
319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_lock_lut()
320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_lock_lut()
325 struct fsl_qspi *q = dev_id; in fsl_qspi_irq_handler() local
329 reg = readl(q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
330 writel(reg, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
333 complete(&q->c); in fsl_qspi_irq_handler()
335 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg); in fsl_qspi_irq_handler()
339 static void fsl_qspi_init_lut(struct fsl_qspi *q) in fsl_qspi_init_lut() argument
341 void __iomem *base = q->iobase; in fsl_qspi_init_lut()
342 int rxfifo = q->devtype_data->rxfifo; in fsl_qspi_init_lut()
347 fsl_qspi_unlock_lut(q); in fsl_qspi_init_lut()
356 if (q->nor_size <= SZ_16M) { in fsl_qspi_init_lut()
379 if (q->nor_size <= SZ_16M) { in fsl_qspi_init_lut()
400 cmd = q->nor[0].erase_opcode; in fsl_qspi_init_lut()
401 addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; in fsl_qspi_init_lut()
438 fsl_qspi_lock_lut(q); in fsl_qspi_init_lut()
442 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) in fsl_qspi_get_seqid() argument
470 if (cmd == q->nor[0].erase_opcode) in fsl_qspi_get_seqid()
472 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); in fsl_qspi_get_seqid()
479 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) in fsl_qspi_runcmd() argument
481 void __iomem *base = q->iobase; in fsl_qspi_runcmd()
486 init_completion(&q->c); in fsl_qspi_runcmd()
487 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n", in fsl_qspi_runcmd()
488 q->chip_base_addr, addr, len, cmd); in fsl_qspi_runcmd()
493 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR); in fsl_qspi_runcmd()
502 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2); in fsl_qspi_runcmd()
509 seqid = fsl_qspi_get_seqid(q, cmd); in fsl_qspi_runcmd()
513 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) { in fsl_qspi_runcmd()
514 dev_err(q->dev, in fsl_qspi_runcmd()
530 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf) in fsl_qspi_read_data() argument
536 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4); in fsl_qspi_read_data()
537 tmp = fsl_qspi_endian_xchg(q, tmp); in fsl_qspi_read_data()
538 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n", in fsl_qspi_read_data()
539 q->chip_base_addr, tmp); in fsl_qspi_read_data()
560 static inline void fsl_qspi_invalid(struct fsl_qspi *q) in fsl_qspi_invalid() argument
564 reg = readl(q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
566 writel(reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
575 writel(reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
578 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, in fsl_qspi_nor_write() argument
585 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n", in fsl_qspi_nor_write()
586 q->chip_base_addr, to, count); in fsl_qspi_nor_write()
589 tmp = readl(q->iobase + QUADSPI_MCR); in fsl_qspi_nor_write()
590 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_nor_write()
594 tmp = fsl_qspi_endian_xchg(q, *txbuf); in fsl_qspi_nor_write()
595 writel(tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
600 if (needs_fill_txfifo(q)) in fsl_qspi_nor_write()
602 writel(tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
605 ret = fsl_qspi_runcmd(q, opcode, to, count); in fsl_qspi_nor_write()
613 static void fsl_qspi_set_map_addr(struct fsl_qspi *q) in fsl_qspi_set_map_addr() argument
615 int nor_size = q->nor_size; in fsl_qspi_set_map_addr()
616 void __iomem *base = q->iobase; in fsl_qspi_set_map_addr()
618 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); in fsl_qspi_set_map_addr()
619 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); in fsl_qspi_set_map_addr()
620 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); in fsl_qspi_set_map_addr()
621 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); in fsl_qspi_set_map_addr()
637 static void fsl_qspi_init_abh_read(struct fsl_qspi *q) in fsl_qspi_init_abh_read() argument
639 void __iomem *base = q->iobase; in fsl_qspi_init_abh_read()
650 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8) in fsl_qspi_init_abh_read()
659 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); in fsl_qspi_init_abh_read()
661 q->iobase + QUADSPI_BFGENCR); in fsl_qspi_init_abh_read()
665 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) in fsl_qspi_clk_prep_enable() argument
669 ret = clk_prepare_enable(q->clk_en); in fsl_qspi_clk_prep_enable()
673 ret = clk_prepare_enable(q->clk); in fsl_qspi_clk_prep_enable()
675 clk_disable_unprepare(q->clk_en); in fsl_qspi_clk_prep_enable()
679 if (needs_wakeup_wait_mode(q)) in fsl_qspi_clk_prep_enable()
680 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0); in fsl_qspi_clk_prep_enable()
686 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) in fsl_qspi_clk_disable_unprep() argument
688 if (needs_wakeup_wait_mode(q)) in fsl_qspi_clk_disable_unprep()
689 pm_qos_remove_request(&q->pm_qos_req); in fsl_qspi_clk_disable_unprep()
691 clk_disable_unprepare(q->clk); in fsl_qspi_clk_disable_unprep()
692 clk_disable_unprepare(q->clk_en); in fsl_qspi_clk_disable_unprep()
697 static int fsl_qspi_nor_setup(struct fsl_qspi *q) in fsl_qspi_nor_setup() argument
699 void __iomem *base = q->iobase; in fsl_qspi_nor_setup()
704 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_nor_setup()
707 ret = clk_set_rate(q->clk, 66000000); in fsl_qspi_nor_setup()
711 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_nor_setup()
721 fsl_qspi_init_lut(q); in fsl_qspi_nor_setup()
738 writel(0xffffffff, q->iobase + QUADSPI_FR); in fsl_qspi_nor_setup()
741 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); in fsl_qspi_nor_setup()
746 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q) in fsl_qspi_nor_setup_last() argument
748 unsigned long rate = q->clk_rate; in fsl_qspi_nor_setup_last()
751 if (needs_4x_clock(q)) in fsl_qspi_nor_setup_last()
755 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_nor_setup_last()
757 ret = clk_set_rate(q->clk, rate); in fsl_qspi_nor_setup_last()
761 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_nor_setup_last()
766 fsl_qspi_init_lut(q); in fsl_qspi_nor_setup_last()
769 fsl_qspi_init_abh_read(q); in fsl_qspi_nor_setup_last()
783 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor) in fsl_qspi_set_base_addr() argument
785 q->chip_base_addr = q->nor_size * (nor - q->nor); in fsl_qspi_set_base_addr()
791 struct fsl_qspi *q = nor->priv; in fsl_qspi_read_reg() local
793 ret = fsl_qspi_runcmd(q, opcode, 0, len); in fsl_qspi_read_reg()
797 fsl_qspi_read_data(q, len, buf); in fsl_qspi_read_reg()
803 struct fsl_qspi *q = nor->priv; in fsl_qspi_write_reg() local
807 ret = fsl_qspi_runcmd(q, opcode, 0, 1); in fsl_qspi_write_reg()
812 fsl_qspi_invalid(q); in fsl_qspi_write_reg()
815 ret = fsl_qspi_nor_write(q, nor, opcode, 0, in fsl_qspi_write_reg()
818 dev_err(q->dev, "invalid cmd %d\n", opcode); in fsl_qspi_write_reg()
828 struct fsl_qspi *q = nor->priv; in fsl_qspi_write() local
830 fsl_qspi_nor_write(q, nor, nor->program_opcode, to, in fsl_qspi_write()
834 fsl_qspi_invalid(q); in fsl_qspi_write()
840 struct fsl_qspi *q = nor->priv; in fsl_qspi_read() local
844 if (!q->ahb_addr) { in fsl_qspi_read()
845 q->memmap_offs = q->chip_base_addr + from; in fsl_qspi_read()
846 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP; in fsl_qspi_read()
848 q->ahb_addr = ioremap_nocache( in fsl_qspi_read()
849 q->memmap_phy + q->memmap_offs, in fsl_qspi_read()
850 q->memmap_len); in fsl_qspi_read()
851 if (!q->ahb_addr) { in fsl_qspi_read()
852 dev_err(q->dev, "ioremap failed\n"); in fsl_qspi_read()
856 } else if (q->chip_base_addr + from < q->memmap_offs in fsl_qspi_read()
857 || q->chip_base_addr + from + len > in fsl_qspi_read()
858 q->memmap_offs + q->memmap_len) { in fsl_qspi_read()
859 iounmap(q->ahb_addr); in fsl_qspi_read()
861 q->memmap_offs = q->chip_base_addr + from; in fsl_qspi_read()
862 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP; in fsl_qspi_read()
863 q->ahb_addr = ioremap_nocache( in fsl_qspi_read()
864 q->memmap_phy + q->memmap_offs, in fsl_qspi_read()
865 q->memmap_len); in fsl_qspi_read()
866 if (!q->ahb_addr) { in fsl_qspi_read()
867 dev_err(q->dev, "ioremap failed\n"); in fsl_qspi_read()
872 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n", in fsl_qspi_read()
873 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, in fsl_qspi_read()
877 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, in fsl_qspi_read()
886 struct fsl_qspi *q = nor->priv; in fsl_qspi_erase() local
890 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs); in fsl_qspi_erase()
892 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0); in fsl_qspi_erase()
896 fsl_qspi_invalid(q); in fsl_qspi_erase()
902 struct fsl_qspi *q = nor->priv; in fsl_qspi_prep() local
905 mutex_lock(&q->lock); in fsl_qspi_prep()
907 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_prep()
911 fsl_qspi_set_base_addr(q, nor); in fsl_qspi_prep()
915 mutex_unlock(&q->lock); in fsl_qspi_prep()
921 struct fsl_qspi *q = nor->priv; in fsl_qspi_unprep() local
923 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_unprep()
924 mutex_unlock(&q->lock); in fsl_qspi_unprep()
932 struct fsl_qspi *q; in fsl_qspi_probe() local
940 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); in fsl_qspi_probe()
941 if (!q) in fsl_qspi_probe()
944 q->nor_num = of_get_child_count(dev->of_node); in fsl_qspi_probe()
945 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP) in fsl_qspi_probe()
948 q->dev = dev; in fsl_qspi_probe()
949 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data; in fsl_qspi_probe()
950 platform_set_drvdata(pdev, q); in fsl_qspi_probe()
954 q->iobase = devm_ioremap_resource(dev, res); in fsl_qspi_probe()
955 if (IS_ERR(q->iobase)) in fsl_qspi_probe()
956 return PTR_ERR(q->iobase); in fsl_qspi_probe()
966 q->memmap_phy = res->start; in fsl_qspi_probe()
969 q->clk_en = devm_clk_get(dev, "qspi_en"); in fsl_qspi_probe()
970 if (IS_ERR(q->clk_en)) in fsl_qspi_probe()
971 return PTR_ERR(q->clk_en); in fsl_qspi_probe()
973 q->clk = devm_clk_get(dev, "qspi"); in fsl_qspi_probe()
974 if (IS_ERR(q->clk)) in fsl_qspi_probe()
975 return PTR_ERR(q->clk); in fsl_qspi_probe()
977 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_probe()
991 fsl_qspi_irq_handler, 0, pdev->name, q); in fsl_qspi_probe()
997 ret = fsl_qspi_nor_setup(q); in fsl_qspi_probe()
1002 q->has_second_chip = true; in fsl_qspi_probe()
1004 mutex_init(&q->lock); in fsl_qspi_probe()
1009 if (!q->has_second_chip) in fsl_qspi_probe()
1012 nor = &q->nor[i]; in fsl_qspi_probe()
1017 nor->priv = q; in fsl_qspi_probe()
1030 &q->clk_rate); in fsl_qspi_probe()
1035 fsl_qspi_set_base_addr(q, nor); in fsl_qspi_probe()
1047 if (q->nor_size == 0) { in fsl_qspi_probe()
1048 q->nor_size = mtd->size; in fsl_qspi_probe()
1051 fsl_qspi_set_map_addr(q); in fsl_qspi_probe()
1063 if (nor->page_size > q->devtype_data->txfifo) in fsl_qspi_probe()
1064 nor->page_size = q->devtype_data->txfifo; in fsl_qspi_probe()
1070 ret = fsl_qspi_nor_setup_last(q); in fsl_qspi_probe()
1074 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_probe()
1078 for (i = 0; i < q->nor_num; i++) { in fsl_qspi_probe()
1080 if (!q->has_second_chip) in fsl_qspi_probe()
1082 mtd_device_unregister(&q->nor[i].mtd); in fsl_qspi_probe()
1085 mutex_destroy(&q->lock); in fsl_qspi_probe()
1087 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_probe()
1095 struct fsl_qspi *q = platform_get_drvdata(pdev); in fsl_qspi_remove() local
1098 for (i = 0; i < q->nor_num; i++) { in fsl_qspi_remove()
1100 if (!q->has_second_chip) in fsl_qspi_remove()
1102 mtd_device_unregister(&q->nor[i].mtd); in fsl_qspi_remove()
1106 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_remove()
1107 writel(0x0, q->iobase + QUADSPI_RSER); in fsl_qspi_remove()
1109 mutex_destroy(&q->lock); in fsl_qspi_remove()
1111 if (q->ahb_addr) in fsl_qspi_remove()
1112 iounmap(q->ahb_addr); in fsl_qspi_remove()
1125 struct fsl_qspi *q = platform_get_drvdata(pdev); in fsl_qspi_resume() local
1127 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_resume()
1131 fsl_qspi_nor_setup(q); in fsl_qspi_resume()
1132 fsl_qspi_set_map_addr(q); in fsl_qspi_resume()
1133 fsl_qspi_nor_setup_last(q); in fsl_qspi_resume()
1135 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_resume()