249 static void bnx2_init_napi(struct bnx2 *bp);
250 static void bnx2_del_napi(struct bnx2 *bp);
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)  in bnx2_tx_avail()  argument
268 	return bp->tx_ring_size - diff;  in bnx2_tx_avail()
272 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)  in bnx2_reg_rd_ind()  argument
276 	spin_lock_bh(&bp->indirect_lock);  in bnx2_reg_rd_ind()
277 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
278 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
279 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_reg_rd_ind()
284 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_reg_wr_ind()  argument
286 	spin_lock_bh(&bp->indirect_lock);  in bnx2_reg_wr_ind()
287 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
288 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
289 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_reg_wr_ind()
293 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_shmem_wr()  argument
295 	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);  in bnx2_shmem_wr()
299 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)  in bnx2_shmem_rd()  argument
301 	return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);  in bnx2_shmem_rd()
305 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)  in bnx2_ctx_wr()  argument
308 	spin_lock_bh(&bp->indirect_lock);  in bnx2_ctx_wr()
309 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_ctx_wr()
312 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
313 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
316 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
322 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
323 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
325 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_ctx_wr()
332 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_drv_ctl()  local
337 		bnx2_reg_wr_ind(bp, io->offset, io->data);  in bnx2_drv_ctl()
340 		io->data = bnx2_reg_rd_ind(bp, io->offset);  in bnx2_drv_ctl()
343 		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);  in bnx2_drv_ctl()
351 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)  in bnx2_setup_cnic_irq_info()  argument
353 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_setup_cnic_irq_info()
354 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_setup_cnic_irq_info()
357 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_setup_cnic_irq_info()
360 		sb_id = bp->irq_nvecs;  in bnx2_setup_cnic_irq_info()
370 	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;  in bnx2_setup_cnic_irq_info()
381 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_register_cnic()  local
382 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_register_cnic()
390 	if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))  in bnx2_register_cnic()
393 	bp->cnic_data = data;  in bnx2_register_cnic()
394 	rcu_assign_pointer(bp->cnic_ops, ops);  in bnx2_register_cnic()
399 	bnx2_setup_cnic_irq_info(bp);  in bnx2_register_cnic()
406 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_unregister_cnic()  local
407 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_unregister_cnic()
408 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_unregister_cnic()
410 	mutex_lock(&bp->cnic_lock);  in bnx2_unregister_cnic()
413 	RCU_INIT_POINTER(bp->cnic_ops, NULL);  in bnx2_unregister_cnic()
414 	mutex_unlock(&bp->cnic_lock);  in bnx2_unregister_cnic()
421 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_cnic_probe()  local
422 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_cnic_probe()
428 	cp->chip_id = bp->chip_id;  in bnx2_cnic_probe()
429 	cp->pdev = bp->pdev;  in bnx2_cnic_probe()
430 	cp->io_base = bp->regview;  in bnx2_cnic_probe()
439 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
444 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_stop()
445 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_stop()
446 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_stop()
449 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_stop()
451 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_stop()
455 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
460 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_start()
461 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_start()
462 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_start()
464 		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_cnic_start()
465 			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_cnic_start()
470 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_start()
472 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_start()
478 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
483 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
490 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)  in bnx2_read_phy()  argument
495 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
496 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
499 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
500 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
505 	val1 = (bp->phy_addr << 21) | (reg << 16) |  in bnx2_read_phy()
508 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
513 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
517 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
533 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
534 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
537 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
538 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)  in bnx2_write_phy()  argument
552 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
553 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
556 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
557 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
562 	val1 = (bp->phy_addr << 21) | (reg << 16) | val |  in bnx2_write_phy()
565 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
570 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
582 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
583 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
586 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
587 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
596 bnx2_disable_int(struct bnx2 *bp)  in bnx2_disable_int()  argument
601 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_disable_int()
602 		bnapi = &bp->bnx2_napi[i];  in bnx2_disable_int()
603 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
606 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
610 bnx2_enable_int(struct bnx2 *bp)  in bnx2_enable_int()  argument
615 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_enable_int()
616 		bnapi = &bp->bnx2_napi[i];  in bnx2_enable_int()
618 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
623 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
627 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
631 bnx2_disable_int_sync(struct bnx2 *bp)  in bnx2_disable_int_sync()  argument
635 	atomic_inc(&bp->intr_sem);  in bnx2_disable_int_sync()
636 	if (!netif_running(bp->dev))  in bnx2_disable_int_sync()
639 	bnx2_disable_int(bp);  in bnx2_disable_int_sync()
640 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_disable_int_sync()
641 		synchronize_irq(bp->irq_tbl[i].vector);  in bnx2_disable_int_sync()
645 bnx2_napi_disable(struct bnx2 *bp)  in bnx2_napi_disable()  argument
649 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_disable()
650 		napi_disable(&bp->bnx2_napi[i].napi);  in bnx2_napi_disable()
654 bnx2_napi_enable(struct bnx2 *bp)  in bnx2_napi_enable()  argument
658 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_enable()
659 		napi_enable(&bp->bnx2_napi[i].napi);  in bnx2_napi_enable()
663 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)  in bnx2_netif_stop()  argument
666 		bnx2_cnic_stop(bp);  in bnx2_netif_stop()
667 	if (netif_running(bp->dev)) {  in bnx2_netif_stop()
668 		bnx2_napi_disable(bp);  in bnx2_netif_stop()
669 		netif_tx_disable(bp->dev);  in bnx2_netif_stop()
671 	bnx2_disable_int_sync(bp);  in bnx2_netif_stop()
672 	netif_carrier_off(bp->dev);	/* prevent tx timeout */  in bnx2_netif_stop()
676 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)  in bnx2_netif_start()  argument
678 	if (atomic_dec_and_test(&bp->intr_sem)) {  in bnx2_netif_start()
679 		if (netif_running(bp->dev)) {  in bnx2_netif_start()
680 			netif_tx_wake_all_queues(bp->dev);  in bnx2_netif_start()
681 			spin_lock_bh(&bp->phy_lock);  in bnx2_netif_start()
682 			if (bp->link_up)  in bnx2_netif_start()
683 				netif_carrier_on(bp->dev);  in bnx2_netif_start()
684 			spin_unlock_bh(&bp->phy_lock);  in bnx2_netif_start()
685 			bnx2_napi_enable(bp);  in bnx2_netif_start()
686 			bnx2_enable_int(bp);  in bnx2_netif_start()
688 				bnx2_cnic_start(bp);  in bnx2_netif_start()
694 bnx2_free_tx_mem(struct bnx2 *bp)  in bnx2_free_tx_mem()  argument
698 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_mem()
699 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_mem()
703 			dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_free_tx_mem()
714 bnx2_free_rx_mem(struct bnx2 *bp)  in bnx2_free_rx_mem()  argument
718 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_mem()
719 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_mem()
723 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_free_rx_mem()
725 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
733 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_free_rx_mem()
735 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
746 bnx2_alloc_tx_mem(struct bnx2 *bp)  in bnx2_alloc_tx_mem()  argument
750 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_alloc_tx_mem()
751 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_tx_mem()
759 			dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_alloc_tx_mem()
768 bnx2_alloc_rx_mem(struct bnx2 *bp)  in bnx2_alloc_rx_mem()  argument
772 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_alloc_rx_mem()
773 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_rx_mem()
778 			vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);  in bnx2_alloc_rx_mem()
782 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_alloc_rx_mem()
784 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
793 		if (bp->rx_pg_ring_size) {  in bnx2_alloc_rx_mem()
795 						  bp->rx_max_pg_ring);  in bnx2_alloc_rx_mem()
801 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_alloc_rx_mem()
803 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
818 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_free_stats_blk()  local
820 	if (bp->status_blk) {  in bnx2_free_stats_blk()
821 		dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_free_stats_blk()
822 				  bp->status_blk,  in bnx2_free_stats_blk()
823 				  bp->status_blk_mapping);  in bnx2_free_stats_blk()
824 		bp->status_blk = NULL;  in bnx2_free_stats_blk()
825 		bp->stats_blk = NULL;  in bnx2_free_stats_blk()
834 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_alloc_stats_blk()  local
838 	if (bp->flags & BNX2_FLAG_MSIX_CAP)  in bnx2_alloc_stats_blk()
841 	bp->status_stats_size = status_blk_size +  in bnx2_alloc_stats_blk()
843 	status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_alloc_stats_blk()
844 					 &bp->status_blk_mapping, GFP_KERNEL);  in bnx2_alloc_stats_blk()
848 	bp->status_blk = status_blk;  in bnx2_alloc_stats_blk()
849 	bp->stats_blk = status_blk + status_blk_size;  in bnx2_alloc_stats_blk()
850 	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;  in bnx2_alloc_stats_blk()
856 bnx2_free_mem(struct bnx2 *bp)  in bnx2_free_mem()  argument
859 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_free_mem()
861 	bnx2_free_tx_mem(bp);  in bnx2_free_mem()
862 	bnx2_free_rx_mem(bp);  in bnx2_free_mem()
864 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_free_mem()
865 		if (bp->ctx_blk[i]) {  in bnx2_free_mem()
866 			dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,  in bnx2_free_mem()
867 					  bp->ctx_blk[i],  in bnx2_free_mem()
868 					  bp->ctx_blk_mapping[i]);  in bnx2_free_mem()
869 			bp->ctx_blk[i] = NULL;  in bnx2_free_mem()
878 bnx2_alloc_mem(struct bnx2 *bp)  in bnx2_alloc_mem()  argument
883 	bnapi = &bp->bnx2_napi[0];  in bnx2_alloc_mem()
884 	bnapi->status_blk.msi = bp->status_blk;  in bnx2_alloc_mem()
889 	if (bp->flags & BNX2_FLAG_MSIX_CAP) {  in bnx2_alloc_mem()
890 		for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_alloc_mem()
893 			bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_mem()
895 			sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);  in bnx2_alloc_mem()
905 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_alloc_mem()
906 		bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;  in bnx2_alloc_mem()
907 		if (bp->ctx_pages == 0)  in bnx2_alloc_mem()
908 			bp->ctx_pages = 1;  in bnx2_alloc_mem()
909 		for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_alloc_mem()
910 			bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_mem()
912 						&bp->ctx_blk_mapping[i],  in bnx2_alloc_mem()
914 			if (bp->ctx_blk[i] == NULL)  in bnx2_alloc_mem()
919 	err = bnx2_alloc_rx_mem(bp);  in bnx2_alloc_mem()
923 	err = bnx2_alloc_tx_mem(bp);  in bnx2_alloc_mem()
930 	bnx2_free_mem(bp);  in bnx2_alloc_mem()
935 bnx2_report_fw_link(struct bnx2 *bp)  in bnx2_report_fw_link()  argument
939 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_report_fw_link()
942 	if (bp->link_up) {  in bnx2_report_fw_link()
945 		switch (bp->line_speed) {  in bnx2_report_fw_link()
947 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
953 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
959 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
965 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
974 		if (bp->autoneg) {  in bnx2_report_fw_link()
977 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
978 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
981 			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)  in bnx2_report_fw_link()
990 	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);  in bnx2_report_fw_link()
994 bnx2_xceiver_str(struct bnx2 *bp)  in bnx2_xceiver_str()  argument
996 	return (bp->phy_port == PORT_FIBRE) ? "SerDes" :  in bnx2_xceiver_str()
997 		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :  in bnx2_xceiver_str()
1002 bnx2_report_link(struct bnx2 *bp)  in bnx2_report_link()  argument
1004 	if (bp->link_up) {  in bnx2_report_link()
1005 		netif_carrier_on(bp->dev);  in bnx2_report_link()
1006 		netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",  in bnx2_report_link()
1007 			    bnx2_xceiver_str(bp),  in bnx2_report_link()
1008 			    bp->line_speed,  in bnx2_report_link()
1009 			    bp->duplex == DUPLEX_FULL ? "full" : "half");  in bnx2_report_link()
1011 		if (bp->flow_ctrl) {  in bnx2_report_link()
1012 			if (bp->flow_ctrl & FLOW_CTRL_RX) {  in bnx2_report_link()
1014 				if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_report_link()
1024 		netif_carrier_off(bp->dev);  in bnx2_report_link()
1025 		netdev_err(bp->dev, "NIC %s Link is Down\n",  in bnx2_report_link()
1026 			   bnx2_xceiver_str(bp));  in bnx2_report_link()
1029 	bnx2_report_fw_link(bp);  in bnx2_report_link()
1033 bnx2_resolve_flow_ctrl(struct bnx2 *bp)  in bnx2_resolve_flow_ctrl()  argument
1037 	bp->flow_ctrl = 0;  in bnx2_resolve_flow_ctrl()
1038 	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_resolve_flow_ctrl()
1041 		if (bp->duplex == DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1042 			bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_resolve_flow_ctrl()
1047 	if (bp->duplex != DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1051 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_resolve_flow_ctrl()
1052 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_resolve_flow_ctrl()
1055 		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_resolve_flow_ctrl()
1057 			bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1059 			bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1063 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_resolve_flow_ctrl()
1064 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_resolve_flow_ctrl()
1066 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_resolve_flow_ctrl()
1087 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1090 				bp->flow_ctrl = FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1095 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1103 			bp->flow_ctrl = FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1109 bnx2_5709s_linkup(struct bnx2 *bp)  in bnx2_5709s_linkup()  argument
1113 	bp->link_up = 1;  in bnx2_5709s_linkup()
1115 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);  in bnx2_5709s_linkup()
1116 	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);  in bnx2_5709s_linkup()
1117 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_5709s_linkup()
1119 	if ((bp->autoneg & AUTONEG_SPEED) == 0) {  in bnx2_5709s_linkup()
1120 		bp->line_speed = bp->req_line_speed;  in bnx2_5709s_linkup()
1121 		bp->duplex = bp->req_duplex;  in bnx2_5709s_linkup()
1127 			bp->line_speed = SPEED_10;  in bnx2_5709s_linkup()
1130 			bp->line_speed = SPEED_100;  in bnx2_5709s_linkup()
1134 			bp->line_speed = SPEED_1000;  in bnx2_5709s_linkup()
1137 			bp->line_speed = SPEED_2500;  in bnx2_5709s_linkup()
1141 		bp->duplex = DUPLEX_FULL;  in bnx2_5709s_linkup()
1143 		bp->duplex = DUPLEX_HALF;  in bnx2_5709s_linkup()
1148 bnx2_5708s_linkup(struct bnx2 *bp)  in bnx2_5708s_linkup()  argument
1152 	bp->link_up = 1;  in bnx2_5708s_linkup()
1153 	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_5708s_linkup()
1156 			bp->line_speed = SPEED_10;  in bnx2_5708s_linkup()
1159 			bp->line_speed = SPEED_100;  in bnx2_5708s_linkup()
1162 			bp->line_speed = SPEED_1000;  in bnx2_5708s_linkup()
1165 			bp->line_speed = SPEED_2500;  in bnx2_5708s_linkup()
1169 		bp->duplex = DUPLEX_FULL;  in bnx2_5708s_linkup()
1171 		bp->duplex = DUPLEX_HALF;  in bnx2_5708s_linkup()
1177 bnx2_5706s_linkup(struct bnx2 *bp)  in bnx2_5706s_linkup()  argument
1181 	bp->link_up = 1;  in bnx2_5706s_linkup()
1182 	bp->line_speed = SPEED_1000;  in bnx2_5706s_linkup()
1184 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706s_linkup()
1186 		bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1189 		bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1196 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_5706s_linkup()
1197 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_5706s_linkup()
1203 			bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1206 			bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1214 bnx2_copper_linkup(struct bnx2 *bp)  in bnx2_copper_linkup()  argument
1218 	bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1220 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_copper_linkup()
1224 		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);  in bnx2_copper_linkup()
1225 		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);  in bnx2_copper_linkup()
1229 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1230 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1233 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1234 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1237 			bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_copper_linkup()
1238 			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_copper_linkup()
1242 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1243 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1246 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1247 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1250 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1251 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1254 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1255 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1258 				bp->line_speed = 0;  in bnx2_copper_linkup()
1259 				bp->link_up = 0;  in bnx2_copper_linkup()
1265 			bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1268 			bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1271 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1274 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1278 	if (bp->link_up) {  in bnx2_copper_linkup()
1281 		bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);  in bnx2_copper_linkup()
1283 			bp->phy_flags |= BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1290 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)  in bnx2_init_rx_context()  argument
1298 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_init_rx_context()
1301 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);  in bnx2_init_rx_context()
1305 bnx2_init_all_rx_contexts(struct bnx2 *bp)  in bnx2_init_all_rx_contexts()  argument
1310 	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {  in bnx2_init_all_rx_contexts()
1313 		bnx2_init_rx_context(bp, cid);  in bnx2_init_all_rx_contexts()
1318 bnx2_set_mac_link(struct bnx2 *bp)  in bnx2_set_mac_link()  argument
1322 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1323 	if (bp->link_up && (bp->line_speed == SPEED_1000) &&  in bnx2_set_mac_link()
1324 		(bp->duplex == DUPLEX_HALF)) {  in bnx2_set_mac_link()
1325 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1329 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1335 	if (bp->link_up) {  in bnx2_set_mac_link()
1336 		switch (bp->line_speed) {  in bnx2_set_mac_link()
1338 				if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {  in bnx2_set_mac_link()
1359 	if (bp->duplex == DUPLEX_HALF)  in bnx2_set_mac_link()
1361 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1364 	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1366 	if (bp->flow_ctrl & FLOW_CTRL_RX)  in bnx2_set_mac_link()
1367 		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1368 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1371 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1374 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_set_mac_link()
1376 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1379 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1381 	bnx2_init_all_rx_contexts(bp);  in bnx2_set_mac_link()
1385 bnx2_enable_bmsr1(struct bnx2 *bp)  in bnx2_enable_bmsr1()  argument
1387 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_enable_bmsr1()
1388 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_enable_bmsr1()
1389 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_bmsr1()
1394 bnx2_disable_bmsr1(struct bnx2 *bp)  in bnx2_disable_bmsr1()  argument
1396 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_disable_bmsr1()
1397 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_disable_bmsr1()
1398 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_bmsr1()
1403 bnx2_test_and_enable_2g5(struct bnx2 *bp)  in bnx2_test_and_enable_2g5()  argument
1408 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_enable_2g5()
1411 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_test_and_enable_2g5()
1412 		bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_test_and_enable_2g5()
1414 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1415 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_enable_2g5()
1417 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_enable_2g5()
1420 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_enable_2g5()
1424 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1425 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_enable_2g5()
1432 bnx2_test_and_disable_2g5(struct bnx2 *bp)  in bnx2_test_and_disable_2g5()  argument
1437 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_disable_2g5()
1440 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1441 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_disable_2g5()
1443 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_disable_2g5()
1446 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_disable_2g5()
1450 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1451 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_disable_2g5()
1458 bnx2_enable_forced_2g5(struct bnx2 *bp)  in bnx2_enable_forced_2g5()  argument
1463 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_enable_forced_2g5()
1466 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_enable_forced_2g5()
1469 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1471 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_enable_forced_2g5()
1475 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_enable_forced_2g5()
1478 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1480 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1482 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_enable_forced_2g5()
1483 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1493 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_enable_forced_2g5()
1495 		if (bp->req_duplex == DUPLEX_FULL)  in bnx2_enable_forced_2g5()
1498 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_enable_forced_2g5()
1502 bnx2_disable_forced_2g5(struct bnx2 *bp)  in bnx2_disable_forced_2g5()  argument
1507 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_disable_forced_2g5()
1510 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_disable_forced_2g5()
1513 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1515 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_disable_forced_2g5()
1517 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_disable_forced_2g5()
1520 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1522 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1524 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_disable_forced_2g5()
1525 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1535 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_disable_forced_2g5()
1537 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_disable_forced_2g5()
1541 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)  in bnx2_5706s_force_link_dn()  argument
1545 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);  in bnx2_5706s_force_link_dn()
1546 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_5706s_force_link_dn()
1548 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);  in bnx2_5706s_force_link_dn()
1550 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);  in bnx2_5706s_force_link_dn()
1554 bnx2_set_link(struct bnx2 *bp)  in bnx2_set_link()  argument
1559 	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {  in bnx2_set_link()
1560 		bp->link_up = 1;  in bnx2_set_link()
1564 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_set_link()
1567 	link_up = bp->link_up;  in bnx2_set_link()
1569 	bnx2_enable_bmsr1(bp);  in bnx2_set_link()
1570 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1571 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1572 	bnx2_disable_bmsr1(bp);  in bnx2_set_link()
1574 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1575 	    (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {  in bnx2_set_link()
1578 		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {  in bnx2_set_link()
1579 			bnx2_5706s_force_link_dn(bp, 0);  in bnx2_set_link()
1580 			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_set_link()
1582 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
1584 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_set_link()
1585 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1586 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1596 		bp->link_up = 1;  in bnx2_set_link()
1598 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_link()
1599 			if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_set_link()
1600 				bnx2_5706s_linkup(bp);  in bnx2_set_link()
1601 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_set_link()
1602 				bnx2_5708s_linkup(bp);  in bnx2_set_link()
1603 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_set_link()
1604 				bnx2_5709s_linkup(bp);  in bnx2_set_link()
1607 			bnx2_copper_linkup(bp);  in bnx2_set_link()
1609 		bnx2_resolve_flow_ctrl(bp);  in bnx2_set_link()
1612 		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1613 		    (bp->autoneg & AUTONEG_SPEED))  in bnx2_set_link()
1614 			bnx2_disable_forced_2g5(bp);  in bnx2_set_link()
1616 		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {  in bnx2_set_link()
1619 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_set_link()
1621 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_set_link()
1623 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_set_link()
1625 		bp->link_up = 0;  in bnx2_set_link()
1628 	if (bp->link_up != link_up) {  in bnx2_set_link()
1629 		bnx2_report_link(bp);  in bnx2_set_link()
1632 	bnx2_set_mac_link(bp);  in bnx2_set_link()
1638 bnx2_reset_phy(struct bnx2 *bp)  in bnx2_reset_phy()  argument
1643         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);  in bnx2_reset_phy()
1649 		bnx2_read_phy(bp, bp->mii_bmcr, &reg);  in bnx2_reset_phy()
1662 bnx2_phy_get_pause_adv(struct bnx2 *bp)  in bnx2_phy_get_pause_adv()  argument
1666 	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==  in bnx2_phy_get_pause_adv()
1669 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1676 	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {  in bnx2_phy_get_pause_adv()
1677 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1684 	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {  in bnx2_phy_get_pause_adv()
1685 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1698 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_remote_phy()  argument
1699 __releases(&bp->phy_lock)  in bnx2_setup_remote_phy()
1700 __acquires(&bp->phy_lock)  in bnx2_setup_remote_phy()
1704 	pause_adv = bnx2_phy_get_pause_adv(bp);  in bnx2_setup_remote_phy()
1706 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_remote_phy()
1708 		if (bp->advertising & ADVERTISED_10baseT_Half)  in bnx2_setup_remote_phy()
1710 		if (bp->advertising & ADVERTISED_10baseT_Full)  in bnx2_setup_remote_phy()
1712 		if (bp->advertising & ADVERTISED_100baseT_Half)  in bnx2_setup_remote_phy()
1714 		if (bp->advertising & ADVERTISED_100baseT_Full)  in bnx2_setup_remote_phy()
1716 		if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_remote_phy()
1718 		if (bp->advertising & ADVERTISED_2500baseX_Full)  in bnx2_setup_remote_phy()
1721 		if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_remote_phy()
1723 		else if (bp->req_line_speed == SPEED_1000)  in bnx2_setup_remote_phy()
1725 		else if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_remote_phy()
1726 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1730 		} else if (bp->req_line_speed == SPEED_10) {  in bnx2_setup_remote_phy()
1731 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1747 	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);  in bnx2_setup_remote_phy()
1749 	spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1750 	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);  in bnx2_setup_remote_phy()
1751 	spin_lock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1757 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_serdes_phy()  argument
1758 __releases(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1759 __acquires(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1764 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_setup_serdes_phy()
1765 		return bnx2_setup_remote_phy(bp, port);  in bnx2_setup_serdes_phy()
1767 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_setup_serdes_phy()
1771 		if (bp->req_line_speed == SPEED_2500) {  in bnx2_setup_serdes_phy()
1772 			if (!bnx2_test_and_enable_2g5(bp))  in bnx2_setup_serdes_phy()
1774 		} else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1775 			if (bnx2_test_and_disable_2g5(bp))  in bnx2_setup_serdes_phy()
1778 		bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1781 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1785 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_serdes_phy()
1786 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1787 				bnx2_enable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1788 			else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1789 				bnx2_disable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1793 		} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_setup_serdes_phy()
1794 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1800 		if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_serdes_phy()
1810 			if (bp->link_up) {  in bnx2_setup_serdes_phy()
1811 				bnx2_write_phy(bp, bp->mii_adv, adv &  in bnx2_setup_serdes_phy()
1814 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |  in bnx2_setup_serdes_phy()
1817 				bp->link_up = 0;  in bnx2_setup_serdes_phy()
1818 				netif_carrier_off(bp->dev);  in bnx2_setup_serdes_phy()
1819 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1820 				bnx2_report_link(bp);  in bnx2_setup_serdes_phy()
1822 			bnx2_write_phy(bp, bp->mii_adv, adv);  in bnx2_setup_serdes_phy()
1823 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1825 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1826 			bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1831 	bnx2_test_and_enable_2g5(bp);  in bnx2_setup_serdes_phy()
1833 	if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_serdes_phy()
1836 	new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_serdes_phy()
1838 	bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1839 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1841 	bp->serdes_an_pending = 0;  in bnx2_setup_serdes_phy()
1844 		if (bp->link_up) {  in bnx2_setup_serdes_phy()
1845 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_serdes_phy()
1846 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1848 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1851 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_serdes_phy()
1852 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |  in bnx2_setup_serdes_phy()
1862 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_setup_serdes_phy()
1863 		bp->serdes_an_pending = 1;  in bnx2_setup_serdes_phy()
1864 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_setup_serdes_phy()
1866 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1867 		bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1874 	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1889 bnx2_set_default_remote_link(struct bnx2 *bp)  in bnx2_set_default_remote_link()  argument
1893 	if (bp->phy_port == PORT_TP)  in bnx2_set_default_remote_link()
1894 		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);  in bnx2_set_default_remote_link()
1896 		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);  in bnx2_set_default_remote_link()
1899 		bp->req_line_speed = 0;  in bnx2_set_default_remote_link()
1900 		bp->autoneg |= AUTONEG_SPEED;  in bnx2_set_default_remote_link()
1901 		bp->advertising = ADVERTISED_Autoneg;  in bnx2_set_default_remote_link()
1903 			bp->advertising |= ADVERTISED_10baseT_Half;  in bnx2_set_default_remote_link()
1905 			bp->advertising |= ADVERTISED_10baseT_Full;  in bnx2_set_default_remote_link()
1907 			bp->advertising |= ADVERTISED_100baseT_Half;  in bnx2_set_default_remote_link()
1909 			bp->advertising |= ADVERTISED_100baseT_Full;  in bnx2_set_default_remote_link()
1911 			bp->advertising |= ADVERTISED_1000baseT_Full;  in bnx2_set_default_remote_link()
1913 			bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_set_default_remote_link()
1915 		bp->autoneg = 0;  in bnx2_set_default_remote_link()
1916 		bp->advertising = 0;  in bnx2_set_default_remote_link()
1917 		bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_remote_link()
1919 			bp->req_line_speed = SPEED_10;  in bnx2_set_default_remote_link()
1921 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1924 			bp->req_line_speed = SPEED_100;  in bnx2_set_default_remote_link()
1926 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1929 			bp->req_line_speed = SPEED_1000;  in bnx2_set_default_remote_link()
1931 			bp->req_line_speed = SPEED_2500;  in bnx2_set_default_remote_link()
1936 bnx2_set_default_link(struct bnx2 *bp)  in bnx2_set_default_link()  argument
1938 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_set_default_link()
1939 		bnx2_set_default_remote_link(bp);  in bnx2_set_default_link()
1943 	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;  in bnx2_set_default_link()
1944 	bp->req_line_speed = 0;  in bnx2_set_default_link()
1945 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_default_link()
1948 		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1950 		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);  in bnx2_set_default_link()
1953 			bp->autoneg = 0;  in bnx2_set_default_link()
1954 			bp->req_line_speed = bp->line_speed = SPEED_1000;  in bnx2_set_default_link()
1955 			bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_link()
1958 		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1962 bnx2_send_heart_beat(struct bnx2 *bp)  in bnx2_send_heart_beat()  argument
1967 	spin_lock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1968 	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);  in bnx2_send_heart_beat()
1969 	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;  in bnx2_send_heart_beat()
1970 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1971 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
1972 	spin_unlock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1976 bnx2_remote_phy_event(struct bnx2 *bp)  in bnx2_remote_phy_event()  argument
1979 	u8 link_up = bp->link_up;  in bnx2_remote_phy_event()
1982 	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_remote_phy_event()
1985 		bnx2_send_heart_beat(bp);  in bnx2_remote_phy_event()
1990 		bp->link_up = 0;  in bnx2_remote_phy_event()
1994 		bp->link_up = 1;  in bnx2_remote_phy_event()
1996 		bp->duplex = DUPLEX_FULL;  in bnx2_remote_phy_event()
1999 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2002 				bp->line_speed = SPEED_10;  in bnx2_remote_phy_event()
2005 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2009 				bp->line_speed = SPEED_100;  in bnx2_remote_phy_event()
2012 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2015 				bp->line_speed = SPEED_1000;  in bnx2_remote_phy_event()
2018 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2021 				bp->line_speed = SPEED_2500;  in bnx2_remote_phy_event()
2024 				bp->line_speed = 0;  in bnx2_remote_phy_event()
2028 		bp->flow_ctrl = 0;  in bnx2_remote_phy_event()
2029 		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_remote_phy_event()
2031 			if (bp->duplex == DUPLEX_FULL)  in bnx2_remote_phy_event()
2032 				bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_remote_phy_event()
2035 				bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_remote_phy_event()
2037 				bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_remote_phy_event()
2040 		old_port = bp->phy_port;  in bnx2_remote_phy_event()
2042 			bp->phy_port = PORT_FIBRE;  in bnx2_remote_phy_event()
2044 			bp->phy_port = PORT_TP;  in bnx2_remote_phy_event()
2046 		if (old_port != bp->phy_port)  in bnx2_remote_phy_event()
2047 			bnx2_set_default_link(bp);  in bnx2_remote_phy_event()
2050 	if (bp->link_up != link_up)  in bnx2_remote_phy_event()
2051 		bnx2_report_link(bp);  in bnx2_remote_phy_event()
2053 	bnx2_set_mac_link(bp);  in bnx2_remote_phy_event()
2057 bnx2_set_remote_link(struct bnx2 *bp)  in bnx2_set_remote_link()  argument
2061 	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);  in bnx2_set_remote_link()
2064 			bnx2_remote_phy_event(bp);  in bnx2_set_remote_link()
2068 			bnx2_send_heart_beat(bp);  in bnx2_set_remote_link()
2075 bnx2_setup_copper_phy(struct bnx2 *bp)  in bnx2_setup_copper_phy()  argument
2076 __releases(&bp->phy_lock)  in bnx2_setup_copper_phy()
2077 __acquires(&bp->phy_lock)  in bnx2_setup_copper_phy()
2082 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_copper_phy()
2084 	bnx2_read_phy(bp, bp->mii_adv, &adv_reg);  in bnx2_setup_copper_phy()
2088 	new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);  in bnx2_setup_copper_phy()
2090 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_copper_phy()
2094 		new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_copper_phy()
2096 		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);  in bnx2_setup_copper_phy()
2099 		new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);  in bnx2_setup_copper_phy()
2104 			bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2105 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);  in bnx2_setup_copper_phy()
2106 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |  in bnx2_setup_copper_phy()
2109 		else if (bp->link_up) {  in bnx2_setup_copper_phy()
2113 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2114 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2121 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2124 	if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_copper_phy()
2127 	if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_copper_phy()
2133 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2134 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2138 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_copper_phy()
2139 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2141 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2143 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2144 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2147 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_copper_phy()
2154 			bp->line_speed = bp->req_line_speed;  in bnx2_setup_copper_phy()
2155 			bp->duplex = bp->req_duplex;  in bnx2_setup_copper_phy()
2156 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2157 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2160 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2161 		bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2167 bnx2_setup_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_phy()  argument
2168 __releases(&bp->phy_lock)  in bnx2_setup_phy()
2169 __acquires(&bp->phy_lock)  in bnx2_setup_phy()
2171 	if (bp->loopback == MAC_LOOPBACK)  in bnx2_setup_phy()
2174 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_setup_phy()
2175 		return bnx2_setup_serdes_phy(bp, port);  in bnx2_setup_phy()
2178 		return bnx2_setup_copper_phy(bp);  in bnx2_setup_phy()
2183 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5709s_phy()  argument
2187 	bp->mii_bmcr = MII_BMCR + 0x10;  in bnx2_init_5709s_phy()
2188 	bp->mii_bmsr = MII_BMSR + 0x10;  in bnx2_init_5709s_phy()
2189 	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;  in bnx2_init_5709s_phy()
2190 	bp->mii_adv = MII_ADVERTISE + 0x10;  in bnx2_init_5709s_phy()
2191 	bp->mii_lpa = MII_LPA + 0x10;  in bnx2_init_5709s_phy()
2192 	bp->mii_up1 = MII_BNX2_OVER1G_UP1;  in bnx2_init_5709s_phy()
2194 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);  in bnx2_init_5709s_phy()
2195 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);  in bnx2_init_5709s_phy()
2197 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2199 		bnx2_reset_phy(bp);  in bnx2_init_5709s_phy()
2201 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);  in bnx2_init_5709s_phy()
2203 	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);  in bnx2_init_5709s_phy()
2206 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);  in bnx2_init_5709s_phy()
2208 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_init_5709s_phy()
2209 	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);  in bnx2_init_5709s_phy()
2210 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_init_5709s_phy()
2214 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);  in bnx2_init_5709s_phy()
2216 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);  in bnx2_init_5709s_phy()
2217 	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);  in bnx2_init_5709s_phy()
2219 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);  in bnx2_init_5709s_phy()
2221 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);  in bnx2_init_5709s_phy()
2225 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);  in bnx2_init_5709s_phy()
2227 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2233 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5708s_phy()  argument
2238 		bnx2_reset_phy(bp);  in bnx2_init_5708s_phy()
2240 	bp->mii_up1 = BCM5708S_UP1;  in bnx2_init_5708s_phy()
2242 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);  in bnx2_init_5708s_phy()
2243 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);  in bnx2_init_5708s_phy()
2244 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2246 	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);  in bnx2_init_5708s_phy()
2248 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);  in bnx2_init_5708s_phy()
2250 	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);  in bnx2_init_5708s_phy()
2252 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);  in bnx2_init_5708s_phy()
2254 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {  in bnx2_init_5708s_phy()
2255 		bnx2_read_phy(bp, BCM5708S_UP1, &val);  in bnx2_init_5708s_phy()
2257 		bnx2_write_phy(bp, BCM5708S_UP1, val);  in bnx2_init_5708s_phy()
2260 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_5708s_phy()
2261 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_5708s_phy()
2262 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {  in bnx2_init_5708s_phy()
2264 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2266 		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);  in bnx2_init_5708s_phy()
2268 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);  in bnx2_init_5708s_phy()
2269 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2272 	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &  in bnx2_init_5708s_phy()
2278 		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_5708s_phy()
2280 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2282 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);  in bnx2_init_5708s_phy()
2283 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2291 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5706s_phy()  argument
2294 		bnx2_reset_phy(bp);  in bnx2_init_5706s_phy()
2296 	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_init_5706s_phy()
2298 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_5706s_phy()
2299 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2301 	if (bp->dev->mtu > 1500) {  in bnx2_init_5706s_phy()
2305 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2306 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2307 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);  in bnx2_init_5706s_phy()
2309 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2310 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2311 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);  in bnx2_init_5706s_phy()
2316 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2317 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2318 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_5706s_phy()
2320 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2321 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2322 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);  in bnx2_init_5706s_phy()
2329 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_copper_phy()  argument
2334 		bnx2_reset_phy(bp);  in bnx2_init_copper_phy()
2336 	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {  in bnx2_init_copper_phy()
2337 		bnx2_write_phy(bp, 0x18, 0x0c00);  in bnx2_init_copper_phy()
2338 		bnx2_write_phy(bp, 0x17, 0x000a);  in bnx2_init_copper_phy()
2339 		bnx2_write_phy(bp, 0x15, 0x310b);  in bnx2_init_copper_phy()
2340 		bnx2_write_phy(bp, 0x17, 0x201f);  in bnx2_init_copper_phy()
2341 		bnx2_write_phy(bp, 0x15, 0x9506);  in bnx2_init_copper_phy()
2342 		bnx2_write_phy(bp, 0x17, 0x401f);  in bnx2_init_copper_phy()
2343 		bnx2_write_phy(bp, 0x15, 0x14e2);  in bnx2_init_copper_phy()
2344 		bnx2_write_phy(bp, 0x18, 0x0400);  in bnx2_init_copper_phy()
2347 	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {  in bnx2_init_copper_phy()
2348 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,  in bnx2_init_copper_phy()
2350 		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_init_copper_phy()
2352 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);  in bnx2_init_copper_phy()
2355 	if (bp->dev->mtu > 1500) {  in bnx2_init_copper_phy()
2357 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2358 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2359 		bnx2_write_phy(bp, 0x18, val | 0x4000);  in bnx2_init_copper_phy()
2361 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2362 		bnx2_write_phy(bp, 0x10, val | 0x1);  in bnx2_init_copper_phy()
2365 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2366 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2367 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_copper_phy()
2369 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2370 		bnx2_write_phy(bp, 0x10, val & ~0x1);  in bnx2_init_copper_phy()
2374 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);  in bnx2_init_copper_phy()
2375 	bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);  in bnx2_init_copper_phy()
2379 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_copper_phy()
2382 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);  in bnx2_init_copper_phy()
2388 bnx2_init_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_phy()  argument
2389 __releases(&bp->phy_lock)  in bnx2_init_phy()
2390 __acquires(&bp->phy_lock)  in bnx2_init_phy()
2395 	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;  in bnx2_init_phy()
2396 	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;  in bnx2_init_phy()
2398 	bp->mii_bmcr = MII_BMCR;  in bnx2_init_phy()
2399 	bp->mii_bmsr = MII_BMSR;  in bnx2_init_phy()
2400 	bp->mii_bmsr1 = MII_BMSR;  in bnx2_init_phy()
2401 	bp->mii_adv = MII_ADVERTISE;  in bnx2_init_phy()
2402 	bp->mii_lpa = MII_LPA;  in bnx2_init_phy()
2404 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2406 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_phy()
2409 	bnx2_read_phy(bp, MII_PHYSID1, &val);  in bnx2_init_phy()
2410 	bp->phy_id = val << 16;  in bnx2_init_phy()
2411 	bnx2_read_phy(bp, MII_PHYSID2, &val);  in bnx2_init_phy()
2412 	bp->phy_id |= val & 0xffff;  in bnx2_init_phy()
2414 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_phy()
2415 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_phy()
2416 			rc = bnx2_init_5706s_phy(bp, reset_phy);  in bnx2_init_phy()
2417 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_phy()
2418 			rc = bnx2_init_5708s_phy(bp, reset_phy);  in bnx2_init_phy()
2419 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_phy()
2420 			rc = bnx2_init_5709s_phy(bp, reset_phy);  in bnx2_init_phy()
2423 		rc = bnx2_init_copper_phy(bp, reset_phy);  in bnx2_init_phy()
2428 		rc = bnx2_setup_phy(bp, bp->phy_port);  in bnx2_init_phy()
2434 bnx2_set_mac_loopback(struct bnx2 *bp)  in bnx2_set_mac_loopback()  argument
2438 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2441 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2442 	bp->link_up = 1;  in bnx2_set_mac_loopback()
2449 bnx2_set_phy_loopback(struct bnx2 *bp)  in bnx2_set_phy_loopback()  argument
2454 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2455 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |  in bnx2_set_phy_loopback()
2457 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2462 		if (bnx2_test_link(bp) == 0)  in bnx2_set_phy_loopback()
2467 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2473 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2474 	bp->link_up = 1;  in bnx2_set_phy_loopback()
2479 bnx2_dump_mcp_state(struct bnx2 *bp)  in bnx2_dump_mcp_state()  argument
2481 	struct net_device *dev = bp->dev;  in bnx2_dump_mcp_state()
2485 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_dump_mcp_state()
2493 		   bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));  in bnx2_dump_mcp_state()
2495 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),  in bnx2_dump_mcp_state()
2496 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),  in bnx2_dump_mcp_state()
2497 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));  in bnx2_dump_mcp_state()
2499 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2500 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2501 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));  in bnx2_dump_mcp_state()
2504 		   bnx2_shmem_rd(bp, BNX2_DRV_MB),  in bnx2_dump_mcp_state()
2505 		   bnx2_shmem_rd(bp, BNX2_FW_MB),  in bnx2_dump_mcp_state()
2506 		   bnx2_shmem_rd(bp, BNX2_LINK_STATUS));  in bnx2_dump_mcp_state()
2507 	pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));  in bnx2_dump_mcp_state()
2509 		   bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),  in bnx2_dump_mcp_state()
2510 		   bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));  in bnx2_dump_mcp_state()
2512 		bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));  in bnx2_dump_mcp_state()
2513 	DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);  in bnx2_dump_mcp_state()
2514 	DP_SHMEM_LINE(bp, 0x3cc);  in bnx2_dump_mcp_state()
2515 	DP_SHMEM_LINE(bp, 0x3dc);  in bnx2_dump_mcp_state()
2516 	DP_SHMEM_LINE(bp, 0x3ec);  in bnx2_dump_mcp_state()
2517 	netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));  in bnx2_dump_mcp_state()
2522 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)  in bnx2_fw_sync()  argument
2527 	bp->fw_wr_seq++;  in bnx2_fw_sync()
2528 	msg_data |= bp->fw_wr_seq;  in bnx2_fw_sync()
2529 	bp->fw_last_msg = msg_data;  in bnx2_fw_sync()
2531 	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2540 		val = bnx2_shmem_rd(bp, BNX2_FW_MB);  in bnx2_fw_sync()
2553 		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2556 			bnx2_dump_mcp_state(bp);  in bnx2_fw_sync()
2569 bnx2_init_5709_context(struct bnx2 *bp)  in bnx2_init_5709_context()  argument
2576 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2578 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2586 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_init_5709_context()
2589 		if (bp->ctx_blk[i])  in bnx2_init_5709_context()
2590 			memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);  in bnx2_init_5709_context()
2594 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2595 			(bp->ctx_blk_mapping[i] & 0xffffffff) |  in bnx2_init_5709_context()
2597 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2598 			(u64) bp->ctx_blk_mapping[i] >> 32);  in bnx2_init_5709_context()
2599 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2603 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
2617 bnx2_init_context(struct bnx2 *bp)  in bnx2_init_context()  argument
2628 		if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_context()
2649 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2650 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2654 				bnx2_ctx_wr(bp, vcid_addr, offset, 0);  in bnx2_init_context()
2660 bnx2_alloc_bad_rbuf(struct bnx2 *bp)  in bnx2_alloc_bad_rbuf()  argument
2670 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2676 	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2678 		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,  in bnx2_alloc_bad_rbuf()
2681 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);  in bnx2_alloc_bad_rbuf()
2691 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2702 		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);  in bnx2_alloc_bad_rbuf()
2709 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)  in bnx2_set_mac_addr()  argument
2715 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2720 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2724 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_page()  argument
2734 	mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,  in bnx2_alloc_rx_page()
2736 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_page()
2749 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)  in bnx2_free_rx_page()  argument
2757 	dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),  in bnx2_free_rx_page()
2765 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_data()  argument
2773 	data = kmalloc(bp->rx_buf_size, gfp);  in bnx2_alloc_rx_data()
2777 	mapping = dma_map_single(&bp->pdev->dev,  in bnx2_alloc_rx_data()
2779 				 bp->rx_buf_use_size,  in bnx2_alloc_rx_data()
2781 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_data()
2792 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_alloc_rx_data()
2798 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)  in bnx2_phy_event_is_set()  argument
2808 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2810 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
2818 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_phy_int()  argument
2820 	spin_lock(&bp->phy_lock);  in bnx2_phy_int()
2822 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))  in bnx2_phy_int()
2823 		bnx2_set_link(bp);  in bnx2_phy_int()
2824 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))  in bnx2_phy_int()
2825 		bnx2_set_remote_link(bp);  in bnx2_phy_int()
2827 	spin_unlock(&bp->phy_lock);  in bnx2_phy_int()
2846 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_tx_int()  argument
2854 	index = (bnapi - bp->bnx2_napi);  in bnx2_tx_int()
2855 	txq = netdev_get_tx_queue(bp->dev, index);  in bnx2_tx_int()
2887 		dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_tx_int()
2899 			dma_unmap_page(&bp->pdev->dev,  in bnx2_tx_int()
2929 		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {  in bnx2_tx_int()
2932 		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))  in bnx2_tx_int()
2941 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_skb_pages()  argument
2999 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_data()  argument
3008 	dma_sync_single_for_device(&bp->pdev->dev,  in bnx2_reuse_rx_data()
3012 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_reuse_rx_data()
3029 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,  in bnx2_rx_skb()  argument
3037 	err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);  in bnx2_rx_skb()
3039 		bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);  in bnx2_rx_skb()
3045 			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_skb()
3050 	dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,  in bnx2_rx_skb()
3080 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,  in bnx2_rx_skb()
3105 			err = bnx2_alloc_rx_page(bp, rxr,  in bnx2_rx_skb()
3111 				bnx2_reuse_rx_skb_pages(bp, rxr, skb,  in bnx2_rx_skb()
3116 			dma_unmap_page(&bp->pdev->dev, mapping_old,  in bnx2_rx_skb()
3148 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_rx_int()  argument
3187 		dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,  in bnx2_rx_int()
3202 		} else if (len > bp->rx_jumbo_thresh) {  in bnx2_rx_int()
3203 			hdr_len = bp->rx_jumbo_thresh;  in bnx2_rx_int()
3213 			bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3220 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_int()
3227 		if (len <= bp->rx_copy_thresh) {  in bnx2_rx_int()
3228 			skb = netdev_alloc_skb(bp->dev, len + 6);  in bnx2_rx_int()
3230 				bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3242 			bnx2_reuse_rx_data(bp, rxr, data,  in bnx2_rx_int()
3246 			skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,  in bnx2_rx_int()
3252 		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))  in bnx2_rx_int()
3255 		skb->protocol = eth_type_trans(skb, bp->dev);  in bnx2_rx_int()
3257 		if (len > (bp->dev->mtu + ETH_HLEN) &&  in bnx2_rx_int()
3267 		if ((bp->dev->features & NETIF_F_RXCSUM) &&  in bnx2_rx_int()
3275 		if ((bp->dev->features & NETIF_F_RXHASH) &&  in bnx2_rx_int()
3281 		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);  in bnx2_rx_int()
3302 		BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_rx_int()
3304 	BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);  in bnx2_rx_int()
3306 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3321 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi()  local
3324 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3329 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi()
3341 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi_1shot()  local
3346 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi_1shot()
3358 	struct bnx2 *bp = bnapi->bp;  in bnx2_interrupt()  local
3368 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3372 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3379 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3382 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_interrupt()
3429 bnx2_chk_missed_msi(struct bnx2 *bp)  in bnx2_chk_missed_msi()  argument
3431 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_chk_missed_msi()
3435 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3439 		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {  in bnx2_chk_missed_msi()
3440 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3442 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3443 			bnx2_msi(bp->irq_tbl[0].vector, bnapi);  in bnx2_chk_missed_msi()
3447 	bp->idle_chk_status_idx = bnapi->last_status_idx;  in bnx2_chk_missed_msi()
3451 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_cnic()  argument
3459 	c_ops = rcu_dereference(bp->cnic_ops);  in bnx2_poll_cnic()
3461 		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,  in bnx2_poll_cnic()
3467 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_link()  argument
3476 		bnx2_phy_int(bp, bnapi);  in bnx2_poll_link()
3481 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3482 			bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_poll_link()
3483 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3487 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,  in bnx2_poll_work()  argument
3494 		bnx2_tx_int(bp, bnapi, 0);  in bnx2_poll_work()
3497 		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);  in bnx2_poll_work()
3505 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll_msix()  local
3510 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll_msix()
3520 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3532 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll()  local
3537 		bnx2_poll_link(bp, bnapi);  in bnx2_poll()
3539 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll()
3542 		bnx2_poll_cnic(bp, bnapi);  in bnx2_poll()
3557 			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {  in bnx2_poll()
3558 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3563 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3568 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3584 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_rx_mode()  local
3592 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3594 	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |  in bnx2_set_rx_mode()
3598 	     (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_set_rx_mode()
3608 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3631 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3646 			bnx2_set_mac_addr(bp, ha->addr,  in bnx2_set_rx_mode()
3655 	if (rx_mode != bp->rx_mode) {  in bnx2_set_rx_mode()
3656 		bp->rx_mode = rx_mode;  in bnx2_set_rx_mode()
3657 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3660 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3661 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3662 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3664 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3694 static void bnx2_release_firmware(struct bnx2 *bp)  in bnx2_release_firmware()  argument
3696 	if (bp->rv2p_firmware) {  in bnx2_release_firmware()
3697 		release_firmware(bp->mips_firmware);  in bnx2_release_firmware()
3698 		release_firmware(bp->rv2p_firmware);  in bnx2_release_firmware()
3699 		bp->rv2p_firmware = NULL;  in bnx2_release_firmware()
3703 static int bnx2_request_uncached_firmware(struct bnx2 *bp)  in bnx2_request_uncached_firmware()  argument
3710 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_request_uncached_firmware()
3712 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||  in bnx2_request_uncached_firmware()
3713 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))  in bnx2_request_uncached_firmware()
3722 	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3728 	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3733 	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_request_uncached_firmware()
3734 	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_request_uncached_firmware()
3735 	if (bp->mips_firmware->size < sizeof(*mips_fw) ||  in bnx2_request_uncached_firmware()
3736 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||  in bnx2_request_uncached_firmware()
3737 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||  in bnx2_request_uncached_firmware()
3738 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||  in bnx2_request_uncached_firmware()
3739 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||  in bnx2_request_uncached_firmware()
3740 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {  in bnx2_request_uncached_firmware()
3745 	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||  in bnx2_request_uncached_firmware()
3746 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||  in bnx2_request_uncached_firmware()
3747 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {  in bnx2_request_uncached_firmware()
3756 	release_firmware(bp->rv2p_firmware);  in bnx2_request_uncached_firmware()
3757 	bp->rv2p_firmware = NULL;  in bnx2_request_uncached_firmware()
3759 	release_firmware(bp->mips_firmware);  in bnx2_request_uncached_firmware()
3763 static int bnx2_request_firmware(struct bnx2 *bp)  in bnx2_request_firmware()  argument
3765 	return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);  in bnx2_request_firmware()
3781 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,  in load_rv2p_fw()  argument
3792 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3803 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3805 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3809 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3812 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3819 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3822 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3825 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3831 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3834 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3841 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,  in load_cpu_fw()  argument
3850 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3852 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3853 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3859 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3866 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3873 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3880 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3887 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3894 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3898 	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);  in load_cpu_fw()
3901 	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);  in load_cpu_fw()
3904 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3906 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3907 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3913 bnx2_init_cpus(struct bnx2 *bp)  in bnx2_init_cpus()  argument
3916 		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_init_cpus()
3918 		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_init_cpus()
3922 	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);  in bnx2_init_cpus()
3923 	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);  in bnx2_init_cpus()
3926 	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);  in bnx2_init_cpus()
3931 	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);  in bnx2_init_cpus()
3936 	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);  in bnx2_init_cpus()
3941 	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);  in bnx2_init_cpus()
3946 	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);  in bnx2_init_cpus()
3953 bnx2_setup_wol(struct bnx2 *bp)  in bnx2_setup_wol()  argument
3958 	if (bp->wol) {  in bnx2_setup_wol()
3962 		autoneg = bp->autoneg;  in bnx2_setup_wol()
3963 		advertising = bp->advertising;  in bnx2_setup_wol()
3965 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3966 			bp->autoneg = AUTONEG_SPEED;  in bnx2_setup_wol()
3967 			bp->advertising = ADVERTISED_10baseT_Half |  in bnx2_setup_wol()
3974 		spin_lock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3975 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_setup_wol()
3976 		spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3978 		bp->autoneg = autoneg;  in bnx2_setup_wol()
3979 		bp->advertising = advertising;  in bnx2_setup_wol()
3981 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_setup_wol()
3983 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
3990 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3994 			if (bp->line_speed == SPEED_2500)  in bnx2_setup_wol()
3998 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
4002 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
4005 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
4008 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
4009 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
4010 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
4013 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
4018 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4020 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4027 	if (!(bp->flags & BNX2_FLAG_NO_WOL)) {  in bnx2_setup_wol()
4031 		if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {  in bnx2_setup_wol()
4032 			bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4038 		val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_setup_wol()
4039 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,  in bnx2_setup_wol()
4041 		bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4042 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);  in bnx2_setup_wol()
4048 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)  in bnx2_set_power_state()  argument
4054 		pci_enable_wake(bp->pdev, PCI_D0, false);  in bnx2_set_power_state()
4055 		pci_set_power_state(bp->pdev, PCI_D0);  in bnx2_set_power_state()
4057 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4060 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4062 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4064 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4068 		bnx2_setup_wol(bp);  in bnx2_set_power_state()
4069 		pci_wake_from_d3(bp->pdev, bp->wol);  in bnx2_set_power_state()
4070 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_set_power_state()
4071 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {  in bnx2_set_power_state()
4073 			if (bp->wol)  in bnx2_set_power_state()
4074 				pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4078 		if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_set_power_state()
4085 			val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_set_power_state()
4088 			bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);  in bnx2_set_power_state()
4090 		pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4104 bnx2_acquire_nvram_lock(struct bnx2 *bp)  in bnx2_acquire_nvram_lock()  argument
4110 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4112 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4126 bnx2_release_nvram_lock(struct bnx2 *bp)  in bnx2_release_nvram_lock()  argument
4132 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4135 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4150 bnx2_enable_nvram_write(struct bnx2 *bp)  in bnx2_enable_nvram_write()  argument
4154 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4155 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4157 	if (bp->flash_info->flags & BNX2_NV_WREN) {  in bnx2_enable_nvram_write()
4160 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4161 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4167 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4179 bnx2_disable_nvram_write(struct bnx2 *bp)  in bnx2_disable_nvram_write()  argument
4183 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4184 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4189 bnx2_enable_nvram_access(struct bnx2 *bp)  in bnx2_enable_nvram_access()  argument
4193 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4195 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4200 bnx2_disable_nvram_access(struct bnx2 *bp)  in bnx2_disable_nvram_access()  argument
4204 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4206 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4212 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)  in bnx2_nvram_erase_page()  argument
4217 	if (bp->flash_info->flags & BNX2_NV_BUFFERED)  in bnx2_nvram_erase_page()
4226 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4229 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4232 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4240 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4252 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)  in bnx2_nvram_read_dword()  argument
4261 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_read_dword()
4262 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_read_dword()
4263 			   bp->flash_info->page_bits) +  in bnx2_nvram_read_dword()
4264 			  (offset % bp->flash_info->page_size);  in bnx2_nvram_read_dword()
4268 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4271 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4274 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4282 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4284 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4297 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)  in bnx2_nvram_write_dword()  argument
4307 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_write_dword()
4308 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_write_dword()
4309 			  bp->flash_info->page_bits) +  in bnx2_nvram_write_dword()
4310 			 (offset % bp->flash_info->page_size);  in bnx2_nvram_write_dword()
4314 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4319 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4322 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4325 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4331 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4341 bnx2_init_nvram(struct bnx2 *bp)  in bnx2_init_nvram()  argument
4347 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_nvram()
4348 		bp->flash_info = &flash_5709;  in bnx2_init_nvram()
4353 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4364 				bp->flash_info = flash;  in bnx2_init_nvram()
4382 				bp->flash_info = flash;  in bnx2_init_nvram()
4385 				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_init_nvram()
4389 				bnx2_enable_nvram_access(bp);  in bnx2_init_nvram()
4392 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4393 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4394 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4395 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4398 				bnx2_disable_nvram_access(bp);  in bnx2_init_nvram()
4399 				bnx2_release_nvram_lock(bp);  in bnx2_init_nvram()
4407 		bp->flash_info = NULL;  in bnx2_init_nvram()
4413 	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);  in bnx2_init_nvram()
4416 		bp->flash_size = val;  in bnx2_init_nvram()
4418 		bp->flash_size = bp->flash_info->total_size;  in bnx2_init_nvram()
4424 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,  in bnx2_nvram_read()  argument
4434 	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_read()
4438 	bnx2_enable_nvram_access(bp);  in bnx2_nvram_read()
4462 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4487 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4500 		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);  in bnx2_nvram_read()
4508 			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);  in bnx2_nvram_read()
4520 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4526 	bnx2_disable_nvram_access(bp);  in bnx2_nvram_read()
4528 	bnx2_release_nvram_lock(bp);  in bnx2_nvram_read()
4534 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,  in bnx2_nvram_write()  argument
4552 		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))  in bnx2_nvram_write()
4559 		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))  in bnx2_nvram_write()
4577 	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4593 		page_start -= (page_start % bp->flash_info->page_size);  in bnx2_nvram_write()
4595 		page_end = page_start + bp->flash_info->page_size;  in bnx2_nvram_write()
4603 		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_write()
4607 		bnx2_enable_nvram_access(bp);  in bnx2_nvram_write()
4610 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4615 			for (j = 0; j < bp->flash_info->page_size; j += 4) {  in bnx2_nvram_write()
4616 				if (j == (bp->flash_info->page_size - 4)) {  in bnx2_nvram_write()
4619 				rc = bnx2_nvram_read_dword(bp,  in bnx2_nvram_write()
4632 		if ((rc = bnx2_enable_nvram_write(bp)) != 0)  in bnx2_nvram_write()
4638 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4640 			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)  in bnx2_nvram_write()
4644 			bnx2_enable_nvram_write(bp);  in bnx2_nvram_write()
4649 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4662 				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&  in bnx2_nvram_write()
4667 			rc = bnx2_nvram_write_dword(bp, addr, buf,  in bnx2_nvram_write()
4679 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4686 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4697 		bnx2_disable_nvram_write(bp);  in bnx2_nvram_write()
4700 		bnx2_disable_nvram_access(bp);  in bnx2_nvram_write()
4701 		bnx2_release_nvram_lock(bp);  in bnx2_nvram_write()
4714 bnx2_init_fw_cap(struct bnx2 *bp)  in bnx2_init_fw_cap()  argument
4718 	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4719 	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4721 	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))  in bnx2_init_fw_cap()
4722 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4724 	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);  in bnx2_init_fw_cap()
4729 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4733 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_init_fw_cap()
4737 		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4739 		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_init_fw_cap()
4741 			bp->phy_port = PORT_FIBRE;  in bnx2_init_fw_cap()
4743 			bp->phy_port = PORT_TP;  in bnx2_init_fw_cap()
4749 	if (netif_running(bp->dev) && sig)  in bnx2_init_fw_cap()
4750 		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);  in bnx2_init_fw_cap()
4754 bnx2_setup_msix_tbl(struct bnx2 *bp)  in bnx2_setup_msix_tbl()  argument
4756 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4758 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4759 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4763 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_chip()  argument
4771 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_reset_chip()
4772 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_reset_chip()
4773 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_reset_chip()
4778 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_reset_chip()
4781 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4783 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_reset_chip()
4784 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4788 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_reset_chip()
4795 	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);  in bnx2_reset_chip()
4799 	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,  in bnx2_reset_chip()
4804 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4806 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_reset_chip()
4807 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4808 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4814 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4822 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4828 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_reset_chip()
4829 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))  in bnx2_reset_chip()
4834 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4849 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4856 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);  in bnx2_reset_chip()
4860 	spin_lock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4861 	old_port = bp->phy_port;  in bnx2_reset_chip()
4862 	bnx2_init_fw_cap(bp);  in bnx2_reset_chip()
4863 	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&  in bnx2_reset_chip()
4864 	    old_port != bp->phy_port)  in bnx2_reset_chip()
4865 		bnx2_set_default_remote_link(bp);  in bnx2_reset_chip()
4866 	spin_unlock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4868 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_reset_chip()
4871 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4874 		rc = bnx2_alloc_bad_rbuf(bp);  in bnx2_reset_chip()
4877 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_reset_chip()
4878 		bnx2_setup_msix_tbl(bp);  in bnx2_reset_chip()
4880 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4888 bnx2_init_chip(struct bnx2 *bp)  in bnx2_init_chip()  argument
4894 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4907 	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))  in bnx2_init_chip()
4910 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&  in bnx2_init_chip()
4911 	    (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&  in bnx2_init_chip()
4912 	    !(bp->flags & BNX2_FLAG_PCIX))  in bnx2_init_chip()
4915 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4917 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_chip()
4918 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4920 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4923 	if (bp->flags & BNX2_FLAG_PCIX) {  in bnx2_init_chip()
4926 		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4928 		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4932 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4939 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4940 		rc = bnx2_init_5709_context(bp);  in bnx2_init_chip()
4944 		bnx2_init_context(bp);  in bnx2_init_chip()
4946 	if ((rc = bnx2_init_cpus(bp)) != 0)  in bnx2_init_chip()
4949 	bnx2_init_nvram(bp);  in bnx2_init_chip()
4951 	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_init_chip()
4953 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4956 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4958 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_chip()
4962 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4965 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4966 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4969 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4972 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
4975 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4977 	val = bp->mac_addr[0] +  in bnx2_init_chip()
4978 	      (bp->mac_addr[1] << 8) +  in bnx2_init_chip()
4979 	      (bp->mac_addr[2] << 16) +  in bnx2_init_chip()
4980 	      bp->mac_addr[3] +  in bnx2_init_chip()
4981 	      (bp->mac_addr[4] << 8) +  in bnx2_init_chip()
4982 	      (bp->mac_addr[5] << 16);  in bnx2_init_chip()
4983 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4986 	mtu = bp->dev->mtu;  in bnx2_init_chip()
4990 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4995 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));  in bnx2_init_chip()
4996 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));  in bnx2_init_chip()
4997 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));  in bnx2_init_chip()
4999 	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);  in bnx2_init_chip()
5001 		bp->bnx2_napi[i].last_status_idx = 0;  in bnx2_init_chip()
5003 	bp->idle_chk_status_idx = 0xffff;  in bnx2_init_chip()
5006 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
5008 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
5009 		(u64) bp->status_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5010 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
5012 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
5013 		(u64) bp->stats_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5014 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
5015 		(u64) bp->stats_blk_mapping >> 32);  in bnx2_init_chip()
5017 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5018 		(bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);  in bnx2_init_chip()
5020 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5021 		(bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);  in bnx2_init_chip()
5023 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5024 		(bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);  in bnx2_init_chip()
5026 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5028 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5030 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5031 		(bp->com_ticks_int << 16) | bp->com_ticks);  in bnx2_init_chip()
5033 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5034 		(bp->cmd_ticks_int << 16) | bp->cmd_ticks);  in bnx2_init_chip()
5036 	if (bp->flags & BNX2_FLAG_BROKEN_STATS)  in bnx2_init_chip()
5037 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5039 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5040 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5042 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)  in bnx2_init_chip()
5049 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_init_chip()
5050 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5056 	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)  in bnx2_init_chip()
5059 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5061 	if (bp->rx_ticks < 25)  in bnx2_init_chip()
5062 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);  in bnx2_init_chip()
5064 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);  in bnx2_init_chip()
5066 	for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_init_chip()
5070 		BNX2_WR(bp, base,  in bnx2_init_chip()
5075 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5076 			(bp->tx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5077 			 bp->tx_quick_cons_trip);  in bnx2_init_chip()
5079 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5080 			(bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5082 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5083 			(bp->rx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5084 			bp->rx_quick_cons_trip);  in bnx2_init_chip()
5086 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5087 			(bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5091 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5093 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5096 	bnx2_set_rx_mode(bp->dev);  in bnx2_init_chip()
5098 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
5099 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5101 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5103 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,  in bnx2_init_chip()
5106 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5107 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5111 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5117 bnx2_clear_ring_states(struct bnx2 *bp)  in bnx2_clear_ring_states()  argument
5125 		bnapi = &bp->bnx2_napi[i];  in bnx2_clear_ring_states()
5140 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)  in bnx2_init_tx_context()  argument
5145 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_tx_context()
5157 	bnx2_ctx_wr(bp, cid_addr, offset0, val);  in bnx2_init_tx_context()
5160 	bnx2_ctx_wr(bp, cid_addr, offset1, val);  in bnx2_init_tx_context()
5163 	bnx2_ctx_wr(bp, cid_addr, offset2, val);  in bnx2_init_tx_context()
5166 	bnx2_ctx_wr(bp, cid_addr, offset3, val);  in bnx2_init_tx_context()
5170 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_tx_ring()  argument
5177 	bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_tx_ring()
5185 	bp->tx_wake_thresh = bp->tx_ring_size / 2;  in bnx2_init_tx_ring()
5198 	bnx2_init_tx_context(bp, cid, txr);  in bnx2_init_tx_ring()
5226 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_rx_ring()  argument
5231 	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_rx_ring()
5242 			     bp->rx_buf_use_size, bp->rx_max_ring);  in bnx2_init_rx_ring()
5244 	bnx2_init_rx_context(bp, cid);  in bnx2_init_rx_ring()
5246 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_rx_ring()
5247 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5248 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5251 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);  in bnx2_init_rx_ring()
5252 	if (bp->rx_pg_ring_size) {  in bnx2_init_rx_ring()
5255 				     PAGE_SIZE, bp->rx_max_pg_ring);  in bnx2_init_rx_ring()
5256 		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;  in bnx2_init_rx_ring()
5257 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);  in bnx2_init_rx_ring()
5258 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,  in bnx2_init_rx_ring()
5262 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5265 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5267 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_rx_ring()
5268 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5272 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5275 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5278 	for (i = 0; i < bp->rx_pg_ring_size; i++) {  in bnx2_init_rx_ring()
5279 		if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5280 			netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",  in bnx2_init_rx_ring()
5281 				    ring_num, i, bp->rx_pg_ring_size);  in bnx2_init_rx_ring()
5290 	for (i = 0; i < bp->rx_ring_size; i++) {  in bnx2_init_rx_ring()
5291 		if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5292 			netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",  in bnx2_init_rx_ring()
5293 				    ring_num, i, bp->rx_ring_size);  in bnx2_init_rx_ring()
5305 	BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_init_rx_ring()
5306 	BNX2_WR16(bp, rxr->rx_bidx_addr, prod);  in bnx2_init_rx_ring()
5308 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5312 bnx2_init_all_rings(struct bnx2 *bp)  in bnx2_init_all_rings()  argument
5317 	bnx2_clear_ring_states(bp);  in bnx2_init_all_rings()
5319 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5320 	for (i = 0; i < bp->num_tx_rings; i++)  in bnx2_init_all_rings()
5321 		bnx2_init_tx_ring(bp, i);  in bnx2_init_all_rings()
5323 	if (bp->num_tx_rings > 1)  in bnx2_init_all_rings()
5324 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5327 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5328 	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);  in bnx2_init_all_rings()
5330 	for (i = 0; i < bp->num_rx_rings; i++)  in bnx2_init_all_rings()
5331 		bnx2_init_rx_ring(bp, i);  in bnx2_init_all_rings()
5333 	if (bp->num_rx_rings > 1) {  in bnx2_init_all_rings()
5339 			tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;  in bnx2_init_all_rings()
5341 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5342 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5353 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5378 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)  in bnx2_set_rx_ring_size()  argument
5383 	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;  in bnx2_set_rx_ring_size()
5388 	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;  in bnx2_set_rx_ring_size()
5389 	bp->rx_pg_ring_size = 0;  in bnx2_set_rx_ring_size()
5390 	bp->rx_max_pg_ring = 0;  in bnx2_set_rx_ring_size()
5391 	bp->rx_max_pg_ring_idx = 0;  in bnx2_set_rx_ring_size()
5392 	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {  in bnx2_set_rx_ring_size()
5393 		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;  in bnx2_set_rx_ring_size()
5399 		bp->rx_pg_ring_size = jumbo_size;  in bnx2_set_rx_ring_size()
5400 		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,  in bnx2_set_rx_ring_size()
5402 		bp->rx_max_pg_ring_idx =  in bnx2_set_rx_ring_size()
5403 			(bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5405 		bp->rx_copy_thresh = 0;  in bnx2_set_rx_ring_size()
5408 	bp->rx_buf_use_size = rx_size;  in bnx2_set_rx_ring_size()
5410 	bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +  in bnx2_set_rx_ring_size()
5412 	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;  in bnx2_set_rx_ring_size()
5413 	bp->rx_ring_size = size;  in bnx2_set_rx_ring_size()
5414 	bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);  in bnx2_set_rx_ring_size()
5415 	bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5419 bnx2_free_tx_skbs(struct bnx2 *bp)  in bnx2_free_tx_skbs()  argument
5423 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_skbs()
5424 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_skbs()
5441 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5452 				dma_unmap_page(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5459 		netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));  in bnx2_free_tx_skbs()
5464 bnx2_free_rx_skbs(struct bnx2 *bp)  in bnx2_free_rx_skbs()  argument
5468 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_skbs()
5469 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_skbs()
5476 		for (j = 0; j < bp->rx_max_ring_idx; j++) {  in bnx2_free_rx_skbs()
5483 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_rx_skbs()
5485 					 bp->rx_buf_use_size,  in bnx2_free_rx_skbs()
5492 		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)  in bnx2_free_rx_skbs()
5493 			bnx2_free_rx_page(bp, rxr, j);  in bnx2_free_rx_skbs()
5498 bnx2_free_skbs(struct bnx2 *bp)  in bnx2_free_skbs()  argument
5500 	bnx2_free_tx_skbs(bp);  in bnx2_free_skbs()
5501 	bnx2_free_rx_skbs(bp);  in bnx2_free_skbs()
5505 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_nic()  argument
5509 	rc = bnx2_reset_chip(bp, reset_code);  in bnx2_reset_nic()
5510 	bnx2_free_skbs(bp);  in bnx2_reset_nic()
5514 	if ((rc = bnx2_init_chip(bp)) != 0)  in bnx2_reset_nic()
5517 	bnx2_init_all_rings(bp);  in bnx2_reset_nic()
5522 bnx2_init_nic(struct bnx2 *bp, int reset_phy)  in bnx2_init_nic()  argument
5526 	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)  in bnx2_init_nic()
5529 	spin_lock_bh(&bp->phy_lock);  in bnx2_init_nic()
5530 	bnx2_init_phy(bp, reset_phy);  in bnx2_init_nic()
5531 	bnx2_set_link(bp);  in bnx2_init_nic()
5532 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_nic()
5533 		bnx2_remote_phy_event(bp);  in bnx2_init_nic()
5534 	spin_unlock_bh(&bp->phy_lock);  in bnx2_init_nic()
5539 bnx2_shutdown_chip(struct bnx2 *bp)  in bnx2_shutdown_chip()  argument
5543 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_shutdown_chip()
5545 	else if (bp->wol)  in bnx2_shutdown_chip()
5550 	return bnx2_reset_chip(bp, reset_code);  in bnx2_shutdown_chip()
5554 bnx2_test_registers(struct bnx2 *bp)  in bnx2_test_registers()  argument
5675 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_registers()
5689 		save_val = readl(bp->regview + offset);  in bnx2_test_registers()
5691 		writel(0, bp->regview + offset);  in bnx2_test_registers()
5693 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5702 		writel(0xffffffff, bp->regview + offset);  in bnx2_test_registers()
5704 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5713 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5717 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5725 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)  in bnx2_do_mem_test()  argument
5736 			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);  in bnx2_do_mem_test()
5738 			if (bnx2_reg_rd_ind(bp, start + offset) !=  in bnx2_do_mem_test()
5748 bnx2_test_memory(struct bnx2 *bp)  in bnx2_test_memory()  argument
5774 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_memory()
5780 		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,  in bnx2_test_memory()
5793 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)  in bnx2_run_loopback()  argument
5805 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;  in bnx2_run_loopback()
5814 		bp->loopback = MAC_LOOPBACK;  in bnx2_run_loopback()
5815 		bnx2_set_mac_loopback(bp);  in bnx2_run_loopback()
5818 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_run_loopback()
5821 		bp->loopback = PHY_LOOPBACK;  in bnx2_run_loopback()
5822 		bnx2_set_phy_loopback(bp);  in bnx2_run_loopback()
5827 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);  in bnx2_run_loopback()
5828 	skb = netdev_alloc_skb(bp->dev, pkt_size);  in bnx2_run_loopback()
5832 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);  in bnx2_run_loopback()
5837 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,  in bnx2_run_loopback()
5839 	if (dma_mapping_error(&bp->pdev->dev, map)) {  in bnx2_run_loopback()
5844 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5845 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5847 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5865 	BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);  in bnx2_run_loopback()
5866 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5870 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5871 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5873 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5877 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);  in bnx2_run_loopback()
5894 	dma_sync_single_for_cpu(&bp->pdev->dev,  in bnx2_run_loopback()
5896 		bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);  in bnx2_run_loopback()
5921 	bp->loopback = 0;  in bnx2_run_loopback()
5931 bnx2_test_loopback(struct bnx2 *bp)  in bnx2_test_loopback()  argument
5935 	if (!netif_running(bp->dev))  in bnx2_test_loopback()
5938 	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_test_loopback()
5939 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5940 	bnx2_init_phy(bp, 1);  in bnx2_test_loopback()
5941 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5942 	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))  in bnx2_test_loopback()
5944 	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))  in bnx2_test_loopback()
5953 bnx2_test_nvram(struct bnx2 *bp)  in bnx2_test_nvram()  argument
5960 	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)  in bnx2_test_nvram()
5969 	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)  in bnx2_test_nvram()
5988 bnx2_test_link(struct bnx2 *bp)  in bnx2_test_link()  argument
5992 	if (!netif_running(bp->dev))  in bnx2_test_link()
5995 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_test_link()
5996 		if (bp->link_up)  in bnx2_test_link()
6000 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_link()
6001 	bnx2_enable_bmsr1(bp);  in bnx2_test_link()
6002 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6003 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6004 	bnx2_disable_bmsr1(bp);  in bnx2_test_link()
6005 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_link()
6014 bnx2_test_intr(struct bnx2 *bp)  in bnx2_test_intr()  argument
6019 	if (!netif_running(bp->dev))  in bnx2_test_intr()
6022 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6025 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6026 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6029 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6045 bnx2_5706_serdes_has_link(struct bnx2 *bp)  in bnx2_5706_serdes_has_link()  argument
6049 	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)  in bnx2_5706_serdes_has_link()
6052 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);  in bnx2_5706_serdes_has_link()
6053 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);  in bnx2_5706_serdes_has_link()
6058 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_has_link()
6059 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6060 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6065 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);  in bnx2_5706_serdes_has_link()
6066 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6067 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6076 bnx2_5706_serdes_timer(struct bnx2 *bp)  in bnx2_5706_serdes_timer()  argument
6080 	spin_lock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6081 	if (bp->serdes_an_pending) {  in bnx2_5706_serdes_timer()
6082 		bp->serdes_an_pending--;  in bnx2_5706_serdes_timer()
6084 	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5706_serdes_timer()
6087 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6089 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6092 			if (bnx2_5706_serdes_has_link(bp)) {  in bnx2_5706_serdes_timer()
6095 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6096 				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6100 	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&  in bnx2_5706_serdes_timer()
6101 		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {  in bnx2_5706_serdes_timer()
6104 		bnx2_write_phy(bp, 0x17, 0x0f01);  in bnx2_5706_serdes_timer()
6105 		bnx2_read_phy(bp, 0x15, &phy2);  in bnx2_5706_serdes_timer()
6109 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6111 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6113 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6116 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6121 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_timer()
6122 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6123 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6125 		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {  in bnx2_5706_serdes_timer()
6126 			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {  in bnx2_5706_serdes_timer()
6127 				bnx2_5706s_force_link_dn(bp, 1);  in bnx2_5706_serdes_timer()
6128 				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_5706_serdes_timer()
6130 				bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6131 		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))  in bnx2_5706_serdes_timer()
6132 			bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6134 	spin_unlock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6138 bnx2_5708_serdes_timer(struct bnx2 *bp)  in bnx2_5708_serdes_timer()  argument
6140 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_5708_serdes_timer()
6143 	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {  in bnx2_5708_serdes_timer()
6144 		bp->serdes_an_pending = 0;  in bnx2_5708_serdes_timer()
6148 	spin_lock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6149 	if (bp->serdes_an_pending)  in bnx2_5708_serdes_timer()
6150 		bp->serdes_an_pending--;  in bnx2_5708_serdes_timer()
6151 	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5708_serdes_timer()
6154 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5708_serdes_timer()
6156 			bnx2_enable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6157 			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;  in bnx2_5708_serdes_timer()
6159 			bnx2_disable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6160 			bp->serdes_an_pending = 2;  in bnx2_5708_serdes_timer()
6161 			bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6165 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6167 	spin_unlock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6173 	struct bnx2 *bp = (struct bnx2 *) data;  in bnx2_timer()  local
6175 	if (!netif_running(bp->dev))  in bnx2_timer()
6178 	if (atomic_read(&bp->intr_sem) != 0)  in bnx2_timer()
6181 	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==  in bnx2_timer()
6183 		bnx2_chk_missed_msi(bp);  in bnx2_timer()
6185 	bnx2_send_heart_beat(bp);  in bnx2_timer()
6187 	bp->stats_blk->stat_FwRxDrop =  in bnx2_timer()
6188 		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);  in bnx2_timer()
6191 	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)  in bnx2_timer()
6192 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6195 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_timer()
6196 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_timer()
6197 			bnx2_5706_serdes_timer(bp);  in bnx2_timer()
6199 			bnx2_5708_serdes_timer(bp);  in bnx2_timer()
6203 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_timer()
6207 bnx2_request_irq(struct bnx2 *bp)  in bnx2_request_irq()  argument
6213 	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)  in bnx2_request_irq()
6218 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_request_irq()
6219 		irq = &bp->irq_tbl[i];  in bnx2_request_irq()
6221 				 &bp->bnx2_napi[i]);  in bnx2_request_irq()
6230 __bnx2_free_irq(struct bnx2 *bp)  in __bnx2_free_irq()  argument
6235 	for (i = 0; i < bp->irq_nvecs; i++) {  in __bnx2_free_irq()
6236 		irq = &bp->irq_tbl[i];  in __bnx2_free_irq()
6238 			free_irq(irq->vector, &bp->bnx2_napi[i]);  in __bnx2_free_irq()
6244 bnx2_free_irq(struct bnx2 *bp)  in bnx2_free_irq()  argument
6247 	__bnx2_free_irq(bp);  in bnx2_free_irq()
6248 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_free_irq()
6249 		pci_disable_msi(bp->pdev);  in bnx2_free_irq()
6250 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_free_irq()
6251 		pci_disable_msix(bp->pdev);  in bnx2_free_irq()
6253 	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);  in bnx2_free_irq()
6257 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)  in bnx2_enable_msix()  argument
6261 	struct net_device *dev = bp->dev;  in bnx2_enable_msix()
6262 	const int len = sizeof(bp->irq_tbl[0].name);  in bnx2_enable_msix()
6264 	bnx2_setup_msix_tbl(bp);  in bnx2_enable_msix()
6265 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6266 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6267 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6271 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6282 	total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,  in bnx2_enable_msix()
6291 	bp->irq_nvecs = msix_vecs;  in bnx2_enable_msix()
6292 	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_enable_msix()
6294 		bp->irq_tbl[i].vector = msix_ent[i].vector;  in bnx2_enable_msix()
6295 		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);  in bnx2_enable_msix()
6296 		bp->irq_tbl[i].handler = bnx2_msi_1shot;  in bnx2_enable_msix()
6301 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)  in bnx2_setup_int_mode()  argument
6306 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6307 		msix_vecs = max(cpus + 1, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6308 	else if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6309 		msix_vecs = max(cpus, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6311 		msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6315 	bp->irq_tbl[0].handler = bnx2_interrupt;  in bnx2_setup_int_mode()
6316 	strcpy(bp->irq_tbl[0].name, bp->dev->name);  in bnx2_setup_int_mode()
6317 	bp->irq_nvecs = 1;  in bnx2_setup_int_mode()
6318 	bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6320 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)  in bnx2_setup_int_mode()
6321 		bnx2_enable_msix(bp, msix_vecs);  in bnx2_setup_int_mode()
6323 	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&  in bnx2_setup_int_mode()
6324 	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_setup_int_mode()
6325 		if (pci_enable_msi(bp->pdev) == 0) {  in bnx2_setup_int_mode()
6326 			bp->flags |= BNX2_FLAG_USING_MSI;  in bnx2_setup_int_mode()
6327 			if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_int_mode()
6328 				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_setup_int_mode()
6329 				bp->irq_tbl[0].handler = bnx2_msi_1shot;  in bnx2_setup_int_mode()
6331 				bp->irq_tbl[0].handler = bnx2_msi;  in bnx2_setup_int_mode()
6333 			bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6337 	if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6338 		bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);  in bnx2_setup_int_mode()
6340 		bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6342 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6343 		bp->num_rx_rings = bp->irq_nvecs;  in bnx2_setup_int_mode()
6345 		bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6347 	netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);  in bnx2_setup_int_mode()
6349 	return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);  in bnx2_setup_int_mode()
6356 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_open()  local
6359 	rc = bnx2_request_firmware(bp);  in bnx2_open()
6365 	bnx2_disable_int(bp);  in bnx2_open()
6367 	rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_open()
6370 	bnx2_init_napi(bp);  in bnx2_open()
6371 	bnx2_napi_enable(bp);  in bnx2_open()
6372 	rc = bnx2_alloc_mem(bp);  in bnx2_open()
6376 	rc = bnx2_request_irq(bp);  in bnx2_open()
6380 	rc = bnx2_init_nic(bp, 1);  in bnx2_open()
6384 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_open()
6386 	atomic_set(&bp->intr_sem, 0);  in bnx2_open()
6388 	memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));  in bnx2_open()
6390 	bnx2_enable_int(bp);  in bnx2_open()
6392 	if (bp->flags & BNX2_FLAG_USING_MSI) {  in bnx2_open()
6396 		if (bnx2_test_intr(bp) != 0) {  in bnx2_open()
6397 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report …  in bnx2_open()
6399 			bnx2_disable_int(bp);  in bnx2_open()
6400 			bnx2_free_irq(bp);  in bnx2_open()
6402 			bnx2_setup_int_mode(bp, 1);  in bnx2_open()
6404 			rc = bnx2_init_nic(bp, 0);  in bnx2_open()
6407 				rc = bnx2_request_irq(bp);  in bnx2_open()
6410 				del_timer_sync(&bp->timer);  in bnx2_open()
6413 			bnx2_enable_int(bp);  in bnx2_open()
6416 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_open()
6418 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_open()
6426 	bnx2_napi_disable(bp);  in bnx2_open()
6427 	bnx2_free_skbs(bp);  in bnx2_open()
6428 	bnx2_free_irq(bp);  in bnx2_open()
6429 	bnx2_free_mem(bp);  in bnx2_open()
6430 	bnx2_del_napi(bp);  in bnx2_open()
6431 	bnx2_release_firmware(bp);  in bnx2_open()
6438 	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);  in bnx2_reset_task()  local
6443 	if (!netif_running(bp->dev)) {  in bnx2_reset_task()
6448 	bnx2_netif_stop(bp, true);  in bnx2_reset_task()
6450 	pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);  in bnx2_reset_task()
6453 		pci_restore_state(bp->pdev);  in bnx2_reset_task()
6454 		pci_save_state(bp->pdev);  in bnx2_reset_task()
6456 	rc = bnx2_init_nic(bp, 1);  in bnx2_reset_task()
6458 		netdev_err(bp->dev, "failed to reset NIC, closing\n");  in bnx2_reset_task()
6459 		bnx2_napi_enable(bp);  in bnx2_reset_task()
6460 		dev_close(bp->dev);  in bnx2_reset_task()
6465 	atomic_set(&bp->intr_sem, 1);  in bnx2_reset_task()
6466 	bnx2_netif_start(bp, true);  in bnx2_reset_task()
6473 bnx2_dump_ftq(struct bnx2 *bp)  in bnx2_dump_ftq()  argument
6477 	struct net_device *dev = bp->dev;  in bnx2_dump_ftq()
6501 			   bnx2_reg_rd_ind(bp, ftq_arr[i].off));  in bnx2_dump_ftq()
6506 			   reg, bnx2_reg_rd_ind(bp, reg),  in bnx2_dump_ftq()
6507 			   bnx2_reg_rd_ind(bp, reg + 4),  in bnx2_dump_ftq()
6508 			   bnx2_reg_rd_ind(bp, reg + 8),  in bnx2_dump_ftq()
6509 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6510 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6511 			   bnx2_reg_rd_ind(bp, reg + 0x20));  in bnx2_dump_ftq()
6516 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6521 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6522 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6524 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6525 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6529 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6530 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6531 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6540 bnx2_dump_state(struct bnx2 *bp)  in bnx2_dump_state()  argument
6542 	struct net_device *dev = bp->dev;  in bnx2_dump_state()
6545 	pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);  in bnx2_dump_state()
6547 		   atomic_read(&bp->intr_sem), val1);  in bnx2_dump_state()
6548 	pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);  in bnx2_dump_state()
6549 	pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);  in bnx2_dump_state()
6552 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6553 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6555 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6557 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6558 	if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_dump_state()
6560 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
6566 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_tx_timeout()  local
6568 	bnx2_dump_ftq(bp);  in bnx2_tx_timeout()
6569 	bnx2_dump_state(bp);  in bnx2_tx_timeout()
6570 	bnx2_dump_mcp_state(bp);  in bnx2_tx_timeout()
6573 	schedule_work(&bp->reset_task);  in bnx2_tx_timeout()
6583 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_start_xmit()  local
6596 	bnapi = &bp->bnx2_napi[i];  in bnx2_start_xmit()
6600 	if (unlikely(bnx2_tx_avail(bp, txr) <  in bnx2_start_xmit()
6655 	mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);  in bnx2_start_xmit()
6656 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_start_xmit()
6684 		mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,  in bnx2_start_xmit()
6686 		if (dma_mapping_error(&bp->pdev->dev, mapping))  in bnx2_start_xmit()
6707 	BNX2_WR16(bp, txr->tx_bidx_addr, prod);  in bnx2_start_xmit()
6708 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
6714 	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {  in bnx2_start_xmit()
6723 		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)  in bnx2_start_xmit()
6737 	dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6745 		dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6758 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_close()  local
6760 	bnx2_disable_int_sync(bp);  in bnx2_close()
6761 	bnx2_napi_disable(bp);  in bnx2_close()
6763 	del_timer_sync(&bp->timer);  in bnx2_close()
6764 	bnx2_shutdown_chip(bp);  in bnx2_close()
6765 	bnx2_free_irq(bp);  in bnx2_close()
6766 	bnx2_free_skbs(bp);  in bnx2_close()
6767 	bnx2_free_mem(bp);  in bnx2_close()
6768 	bnx2_del_napi(bp);  in bnx2_close()
6769 	bp->link_up = 0;  in bnx2_close()
6770 	netif_carrier_off(bp->dev);  in bnx2_close()
6775 bnx2_save_stats(struct bnx2 *bp)  in bnx2_save_stats()  argument
6777 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_save_stats()
6778 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_save_stats()
6802 	GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +		\
6803 	GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6806 	(unsigned long) (bp->stats_blk->ctr +			\
6807 			 bp->temp_stats_blk->ctr)
6812 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_stats64()  local
6814 	if (bp->stats_blk == NULL)  in bnx2_get_stats64()
6861 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_get_stats64()
6862 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_stats64()
6887 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_settings()  local
6891 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_get_settings()
6894 	} else if (bp->phy_port == PORT_FIBRE)  in bnx2_get_settings()
6902 		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_get_settings()
6916 	spin_lock_bh(&bp->phy_lock);  in bnx2_get_settings()
6917 	cmd->port = bp->phy_port;  in bnx2_get_settings()
6918 	cmd->advertising = bp->advertising;  in bnx2_get_settings()
6920 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_get_settings()
6927 		ethtool_cmd_speed_set(cmd, bp->line_speed);  in bnx2_get_settings()
6928 		cmd->duplex = bp->duplex;  in bnx2_get_settings()
6929 		if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {  in bnx2_get_settings()
6930 			if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)  in bnx2_get_settings()
6940 	spin_unlock_bh(&bp->phy_lock);  in bnx2_get_settings()
6943 	cmd->phy_address = bp->phy_addr;  in bnx2_get_settings()
6951 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_settings()  local
6952 	u8 autoneg = bp->autoneg;  in bnx2_set_settings()
6953 	u8 req_duplex = bp->req_duplex;  in bnx2_set_settings()
6954 	u16 req_line_speed = bp->req_line_speed;  in bnx2_set_settings()
6955 	u32 advertising = bp->advertising;  in bnx2_set_settings()
6958 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_settings()
6963 	if (cmd->port != bp->phy_port &&  in bnx2_set_settings()
6964 	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))  in bnx2_set_settings()
6970 	if (!netif_running(dev) && cmd->port != bp->phy_port)  in bnx2_set_settings()
6997 			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_set_settings()
7008 	bp->autoneg = autoneg;  in bnx2_set_settings()
7009 	bp->advertising = advertising;  in bnx2_set_settings()
7010 	bp->req_line_speed = req_line_speed;  in bnx2_set_settings()
7011 	bp->req_duplex = req_duplex;  in bnx2_set_settings()
7018 		err = bnx2_setup_phy(bp, cmd->port);  in bnx2_set_settings()
7021 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_settings()
7029 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_drvinfo()  local
7033 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));  in bnx2_get_drvinfo()
7034 	strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));  in bnx2_get_drvinfo()
7050 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_regs()  local
7080 	if (!netif_running(bp->dev))  in bnx2_get_regs()
7087 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7100 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_wol()  local
7102 	if (bp->flags & BNX2_FLAG_NO_WOL) {  in bnx2_get_wol()
7108 		if (bp->wol)  in bnx2_get_wol()
7119 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_wol()  local
7125 		if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_set_wol()
7128 		bp->wol = 1;  in bnx2_set_wol()
7131 		bp->wol = 0;  in bnx2_set_wol()
7134 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_set_wol()
7142 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_nway_reset()  local
7148 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_nway_reset()
7152 	spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7154 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_nway_reset()
7157 		rc = bnx2_setup_remote_phy(bp, bp->phy_port);  in bnx2_nway_reset()
7158 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7163 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_nway_reset()
7164 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_nway_reset()
7165 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7169 		spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7171 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_nway_reset()
7172 		bp->serdes_an_pending = 1;  in bnx2_nway_reset()
7173 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_nway_reset()
7176 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_nway_reset()
7178 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);  in bnx2_nway_reset()
7180 	spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7188 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link()  local
7190 	return bp->link_up;  in bnx2_get_link()
7196 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom_len()  local
7198 	if (bp->flash_info == NULL)  in bnx2_get_eeprom_len()
7201 	return (int) bp->flash_size;  in bnx2_get_eeprom_len()
7208 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom()  local
7213 	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_get_eeprom()
7222 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_eeprom()  local
7227 	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_set_eeprom()
7235 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_coalesce()  local
7239 	coal->rx_coalesce_usecs = bp->rx_ticks;  in bnx2_get_coalesce()
7240 	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;  in bnx2_get_coalesce()
7241 	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;  in bnx2_get_coalesce()
7242 	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;  in bnx2_get_coalesce()
7244 	coal->tx_coalesce_usecs = bp->tx_ticks;  in bnx2_get_coalesce()
7245 	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;  in bnx2_get_coalesce()
7246 	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;  in bnx2_get_coalesce()
7247 	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;  in bnx2_get_coalesce()
7249 	coal->stats_block_coalesce_usecs = bp->stats_ticks;  in bnx2_get_coalesce()
7257 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_coalesce()  local
7259 	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;  in bnx2_set_coalesce()
7260 	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;  in bnx2_set_coalesce()
7262 	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;  in bnx2_set_coalesce()
7263 	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7265 	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7266 	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7268 	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7269 	if (bp->rx_quick_cons_trip_int > 0xff)  in bnx2_set_coalesce()
7270 		bp->rx_quick_cons_trip_int = 0xff;  in bnx2_set_coalesce()
7272 	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;  in bnx2_set_coalesce()
7273 	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;  in bnx2_set_coalesce()
7275 	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;  in bnx2_set_coalesce()
7276 	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7278 	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7279 	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7281 	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7282 	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =  in bnx2_set_coalesce()
7285 	bp->stats_ticks = coal->stats_block_coalesce_usecs;  in bnx2_set_coalesce()
7286 	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {  in bnx2_set_coalesce()
7287 		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)  in bnx2_set_coalesce()
7288 			bp->stats_ticks = USEC_PER_SEC;  in bnx2_set_coalesce()
7290 	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)  in bnx2_set_coalesce()
7291 		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7292 	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7294 	if (netif_running(bp->dev)) {  in bnx2_set_coalesce()
7295 		bnx2_netif_stop(bp, true);  in bnx2_set_coalesce()
7296 		bnx2_init_nic(bp, 0);  in bnx2_set_coalesce()
7297 		bnx2_netif_start(bp, true);  in bnx2_set_coalesce()
7306 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ringparam()  local
7311 	ering->rx_pending = bp->rx_ring_size;  in bnx2_get_ringparam()
7312 	ering->rx_jumbo_pending = bp->rx_pg_ring_size;  in bnx2_get_ringparam()
7315 	ering->tx_pending = bp->tx_ring_size;  in bnx2_get_ringparam()
7319 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)  in bnx2_change_ring_size()  argument
7321 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7323 		bnx2_save_stats(bp);  in bnx2_change_ring_size()
7325 		bnx2_netif_stop(bp, true);  in bnx2_change_ring_size()
7326 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_change_ring_size()
7328 			bnx2_free_irq(bp);  in bnx2_change_ring_size()
7329 			bnx2_del_napi(bp);  in bnx2_change_ring_size()
7331 			__bnx2_free_irq(bp);  in bnx2_change_ring_size()
7333 		bnx2_free_skbs(bp);  in bnx2_change_ring_size()
7334 		bnx2_free_mem(bp);  in bnx2_change_ring_size()
7337 	bnx2_set_rx_ring_size(bp, rx);  in bnx2_change_ring_size()
7338 	bp->tx_ring_size = tx;  in bnx2_change_ring_size()
7340 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7344 			rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_change_ring_size()
7345 			bnx2_init_napi(bp);  in bnx2_change_ring_size()
7349 			rc = bnx2_alloc_mem(bp);  in bnx2_change_ring_size()
7352 			rc = bnx2_request_irq(bp);  in bnx2_change_ring_size()
7355 			rc = bnx2_init_nic(bp, 0);  in bnx2_change_ring_size()
7358 			bnx2_napi_enable(bp);  in bnx2_change_ring_size()
7359 			dev_close(bp->dev);  in bnx2_change_ring_size()
7363 		mutex_lock(&bp->cnic_lock);  in bnx2_change_ring_size()
7365 		if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)  in bnx2_change_ring_size()
7366 			bnx2_setup_cnic_irq_info(bp);  in bnx2_change_ring_size()
7367 		mutex_unlock(&bp->cnic_lock);  in bnx2_change_ring_size()
7369 		bnx2_netif_start(bp, true);  in bnx2_change_ring_size()
7377 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_ringparam()  local
7386 	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,  in bnx2_set_ringparam()
7394 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_pauseparam()  local
7396 	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);  in bnx2_get_pauseparam()
7397 	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);  in bnx2_get_pauseparam()
7398 	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);  in bnx2_get_pauseparam()
7404 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_pauseparam()  local
7406 	bp->req_flow_ctrl = 0;  in bnx2_set_pauseparam()
7408 		bp->req_flow_ctrl |= FLOW_CTRL_RX;  in bnx2_set_pauseparam()
7410 		bp->req_flow_ctrl |= FLOW_CTRL_TX;  in bnx2_set_pauseparam()
7413 		bp->autoneg |= AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7416 		bp->autoneg &= ~AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7420 		spin_lock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7421 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_set_pauseparam()
7422 		spin_unlock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7582 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_self_test()  local
7588 		bnx2_netif_stop(bp, true);  in bnx2_self_test()
7589 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);  in bnx2_self_test()
7590 		bnx2_free_skbs(bp);  in bnx2_self_test()
7592 		if (bnx2_test_registers(bp) != 0) {  in bnx2_self_test()
7596 		if (bnx2_test_memory(bp) != 0) {  in bnx2_self_test()
7600 		if ((buf[2] = bnx2_test_loopback(bp)) != 0)  in bnx2_self_test()
7603 		if (!netif_running(bp->dev))  in bnx2_self_test()
7604 			bnx2_shutdown_chip(bp);  in bnx2_self_test()
7606 			bnx2_init_nic(bp, 1);  in bnx2_self_test()
7607 			bnx2_netif_start(bp, true);  in bnx2_self_test()
7612 			if (bp->link_up)  in bnx2_self_test()
7618 	if (bnx2_test_nvram(bp) != 0) {  in bnx2_self_test()
7622 	if (bnx2_test_intr(bp) != 0) {  in bnx2_self_test()
7627 	if (bnx2_test_link(bp) != 0) {  in bnx2_self_test()
7653 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ethtool_stats()  local
7655 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_get_ethtool_stats()
7656 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_get_ethtool_stats()
7664 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_get_ethtool_stats()
7665 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||  in bnx2_get_ethtool_stats()
7666 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||  in bnx2_get_ethtool_stats()
7667 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_ethtool_stats()
7699 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_phys_id()  local
7703 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7704 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7708 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7717 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7721 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7722 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
7732 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_features()  local
7741 	    !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&  in bnx2_set_features()
7743 		bnx2_netif_stop(bp, false);  in bnx2_set_features()
7746 		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);  in bnx2_set_features()
7747 		bnx2_netif_start(bp, false);  in bnx2_set_features()
7757 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_channels()  local
7761 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_get_channels()
7770 	channels->rx_count = bp->num_rx_rings;  in bnx2_get_channels()
7771 	channels->tx_count = bp->num_tx_rings;  in bnx2_get_channels()
7779 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_channels()  local
7784 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_set_channels()
7792 	bp->num_req_rx_rings = channels->rx_count;  in bnx2_set_channels()
7793 	bp->num_req_tx_rings = channels->tx_count;  in bnx2_set_channels()
7796 		rc = bnx2_change_ring_size(bp, bp->rx_ring_size,  in bnx2_set_channels()
7797 					   bp->tx_ring_size, true);  in bnx2_set_channels()
7835 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_ioctl()  local
7840 		data->phy_id = bp->phy_addr;  in bnx2_ioctl()
7846 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7852 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7853 		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);  in bnx2_ioctl()
7854 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7862 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7868 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7869 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);  in bnx2_ioctl()
7870 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7886 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mac_addr()  local
7893 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_change_mac_addr()
7902 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mtu()  local
7909 	return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,  in bnx2_change_mtu()
7917 	struct bnx2 *bp = netdev_priv(dev);  in poll_bnx2()  local
7920 	for (i = 0; i < bp->irq_nvecs; i++) {  in poll_bnx2()
7921 		struct bnx2_irq *irq = &bp->irq_tbl[i];  in poll_bnx2()
7924 		irq->handler(irq->vector, &bp->bnx2_napi[i]);  in poll_bnx2()
7931 bnx2_get_5709_media(struct bnx2 *bp)  in bnx2_get_5709_media()  argument
7933 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7940 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7949 	if (bp->func == 0) {  in bnx2_get_5709_media()
7954 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7962 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7969 bnx2_get_pci_speed(struct bnx2 *bp)  in bnx2_get_pci_speed()  argument
7973 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7977 		bp->flags |= BNX2_FLAG_PCIX;  in bnx2_get_pci_speed()
7979 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
7984 			bp->bus_speed_mhz = 133;  in bnx2_get_pci_speed()
7988 			bp->bus_speed_mhz = 100;  in bnx2_get_pci_speed()
7993 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
7998 			bp->bus_speed_mhz = 50;  in bnx2_get_pci_speed()
8004 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8010 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8012 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8016 		bp->flags |= BNX2_FLAG_PCI_32BIT;  in bnx2_get_pci_speed()
8021 bnx2_read_vpd_fw_ver(struct bnx2 *bp)  in bnx2_read_vpd_fw_ver()  argument
8035 	rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,  in bnx2_read_vpd_fw_ver()
8081 	memcpy(bp->fw_version, &data[j], len);  in bnx2_read_vpd_fw_ver()
8082 	bp->fw_version[len] = ' ';  in bnx2_read_vpd_fw_ver()
8091 	struct bnx2 *bp;  in bnx2_init_board()  local
8098 	bp = netdev_priv(dev);  in bnx2_init_board()
8100 	bp->flags = 0;  in bnx2_init_board()
8101 	bp->phy_flags = 0;  in bnx2_init_board()
8103 	bp->temp_stats_blk =  in bnx2_init_board()
8106 	if (bp->temp_stats_blk == NULL) {  in bnx2_init_board()
8133 	bp->pm_cap = pdev->pm_cap;  in bnx2_init_board()
8134 	if (bp->pm_cap == 0) {  in bnx2_init_board()
8141 	bp->dev = dev;  in bnx2_init_board()
8142 	bp->pdev = pdev;  in bnx2_init_board()
8144 	spin_lock_init(&bp->phy_lock);  in bnx2_init_board()
8145 	spin_lock_init(&bp->indirect_lock);  in bnx2_init_board()
8147 	mutex_init(&bp->cnic_lock);  in bnx2_init_board()
8149 	INIT_WORK(&bp->reset_task, bnx2_reset_task);  in bnx2_init_board()
8151 	bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +  in bnx2_init_board()
8153 	if (!bp->regview) {  in bnx2_init_board()
8163 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8167 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8169 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_board()
8175 		bp->flags |= BNX2_FLAG_PCIE;  in bnx2_init_board()
8176 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_board()
8177 			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;  in bnx2_init_board()
8182 			bp->flags |= BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8185 		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);  in bnx2_init_board()
8186 		if (bp->pcix_cap == 0) {  in bnx2_init_board()
8192 		bp->flags |= BNX2_FLAG_BROKEN_STATS;  in bnx2_init_board()
8195 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8196 	    BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {  in bnx2_init_board()
8198 			bp->flags |= BNX2_FLAG_MSIX_CAP;  in bnx2_init_board()
8201 	if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&  in bnx2_init_board()
8202 	    BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {  in bnx2_init_board()
8204 			bp->flags |= BNX2_FLAG_MSI_CAP;  in bnx2_init_board()
8208 	if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8227 	if (!(bp->flags & BNX2_FLAG_PCIE))  in bnx2_init_board()
8228 		bnx2_get_pci_speed(bp);  in bnx2_init_board()
8231 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8232 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8234 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()
8235 	} else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&  in bnx2_init_board()
8236 		!(bp->flags & BNX2_FLAG_PCIX)) {  in bnx2_init_board()
8243 	bnx2_init_nvram(bp);  in bnx2_init_board()
8245 	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);  in bnx2_init_board()
8247 	if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)  in bnx2_init_board()
8248 		bp->func = 1;  in bnx2_init_board()
8252 		u32 off = bp->func << 2;  in bnx2_init_board()
8254 		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);  in bnx2_init_board()
8256 		bp->shmem_base = HOST_VIEW_SHMEM_BASE;  in bnx2_init_board()
8261 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);  in bnx2_init_board()
8270 	bnx2_read_vpd_fw_ver(bp);  in bnx2_init_board()
8272 	j = strlen(bp->fw_version);  in bnx2_init_board()
8273 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);  in bnx2_init_board()
8278 			bp->fw_version[j++] = 'b';  in bnx2_init_board()
8279 			bp->fw_version[j++] = 'c';  in bnx2_init_board()
8280 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8285 				bp->fw_version[j++] = (num / k) + '0';  in bnx2_init_board()
8290 			bp->fw_version[j++] = '.';  in bnx2_init_board()
8292 	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_init_board()
8294 		bp->wol = 1;  in bnx2_init_board()
8297 		bp->flags |= BNX2_FLAG_ASF_ENABLE;  in bnx2_init_board()
8300 			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8306 	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8310 		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);  in bnx2_init_board()
8313 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8315 			reg = bnx2_reg_rd_ind(bp, addr + i * 4);  in bnx2_init_board()
8317 			memcpy(&bp->fw_version[j], &reg, 4);  in bnx2_init_board()
8322 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);  in bnx2_init_board()
8323 	bp->mac_addr[0] = (u8) (reg >> 8);  in bnx2_init_board()
8324 	bp->mac_addr[1] = (u8) reg;  in bnx2_init_board()
8326 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);  in bnx2_init_board()
8327 	bp->mac_addr[2] = (u8) (reg >> 24);  in bnx2_init_board()
8328 	bp->mac_addr[3] = (u8) (reg >> 16);  in bnx2_init_board()
8329 	bp->mac_addr[4] = (u8) (reg >> 8);  in bnx2_init_board()
8330 	bp->mac_addr[5] = (u8) reg;  in bnx2_init_board()
8332 	bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;  in bnx2_init_board()
8333 	bnx2_set_rx_ring_size(bp, 255);  in bnx2_init_board()
8335 	bp->tx_quick_cons_trip_int = 2;  in bnx2_init_board()
8336 	bp->tx_quick_cons_trip = 20;  in bnx2_init_board()
8337 	bp->tx_ticks_int = 18;  in bnx2_init_board()
8338 	bp->tx_ticks = 80;  in bnx2_init_board()
8340 	bp->rx_quick_cons_trip_int = 2;  in bnx2_init_board()
8341 	bp->rx_quick_cons_trip = 12;  in bnx2_init_board()
8342 	bp->rx_ticks_int = 18;  in bnx2_init_board()
8343 	bp->rx_ticks = 18;  in bnx2_init_board()
8345 	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_init_board()
8347 	bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_init_board()
8349 	bp->phy_addr = 1;  in bnx2_init_board()
8357 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_board()
8358 		bnx2_get_5709_media(bp);  in bnx2_init_board()
8359 	else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)  in bnx2_init_board()
8360 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_init_board()
8362 	bp->phy_port = PORT_TP;  in bnx2_init_board()
8363 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_board()
8364 		bp->phy_port = PORT_FIBRE;  in bnx2_init_board()
8365 		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_board()
8367 			bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8368 			bp->wol = 0;  in bnx2_init_board()
8370 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {  in bnx2_init_board()
8377 				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;  in bnx2_init_board()
8379 			bp->phy_addr = 2;  in bnx2_init_board()
8381 				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;  in bnx2_init_board()
8383 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||  in bnx2_init_board()
8384 		   BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8385 		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;  in bnx2_init_board()
8386 	else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8387 		 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||  in bnx2_init_board()
8388 		  BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))  in bnx2_init_board()
8389 		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;  in bnx2_init_board()
8391 	bnx2_init_fw_cap(bp);  in bnx2_init_board()
8393 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_board()
8394 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_board()
8395 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||  in bnx2_init_board()
8396 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()
8397 		bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8398 		bp->wol = 0;  in bnx2_init_board()
8401 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_init_board()
8402 		device_set_wakeup_capable(&bp->pdev->dev, false);  in bnx2_init_board()
8404 		device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_init_board()
8406 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8407 		bp->tx_quick_cons_trip_int =  in bnx2_init_board()
8408 			bp->tx_quick_cons_trip;  in bnx2_init_board()
8409 		bp->tx_ticks_int = bp->tx_ticks;  in bnx2_init_board()
8410 		bp->rx_quick_cons_trip_int =  in bnx2_init_board()
8411 			bp->rx_quick_cons_trip;  in bnx2_init_board()
8412 		bp->rx_ticks_int = bp->rx_ticks;  in bnx2_init_board()
8413 		bp->comp_prod_trip_int = bp->comp_prod_trip;  in bnx2_init_board()
8414 		bp->com_ticks_int = bp->com_ticks;  in bnx2_init_board()
8415 		bp->cmd_ticks_int = bp->cmd_ticks;  in bnx2_init_board()
8428 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {  in bnx2_init_board()
8444 	bnx2_set_default_link(bp);  in bnx2_init_board()
8445 	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in bnx2_init_board()
8447 	init_timer(&bp->timer);  in bnx2_init_board()
8448 	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);  in bnx2_init_board()
8449 	bp->timer.data = (unsigned long) bp;  in bnx2_init_board()
8450 	bp->timer.function = bnx2_timer;  in bnx2_init_board()
8453 	if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)  in bnx2_init_board()
8454 		bp->cnic_eth_dev.max_iscsi_conn =  in bnx2_init_board()
8455 			(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &  in bnx2_init_board()
8457 	bp->cnic_probe = bnx2_cnic_probe;  in bnx2_init_board()
8464 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_init_board()
8466 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8469 	pci_iounmap(pdev, bp->regview);  in bnx2_init_board()
8470 	bp->regview = NULL;  in bnx2_init_board()
8479 	kfree(bp->temp_stats_blk);  in bnx2_init_board()
8485 bnx2_bus_string(struct bnx2 *bp, char *str)  in bnx2_bus_string()  argument
8489 	if (bp->flags & BNX2_FLAG_PCIE) {  in bnx2_bus_string()
8493 		if (bp->flags & BNX2_FLAG_PCIX)  in bnx2_bus_string()
8495 		if (bp->flags & BNX2_FLAG_PCI_32BIT)  in bnx2_bus_string()
8499 		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);  in bnx2_bus_string()
8505 bnx2_del_napi(struct bnx2 *bp)  in bnx2_del_napi()  argument
8509 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_del_napi()
8510 		netif_napi_del(&bp->bnx2_napi[i].napi);  in bnx2_del_napi()
8514 bnx2_init_napi(struct bnx2 *bp)  in bnx2_init_napi()  argument
8518 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_init_napi()
8519 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_init_napi()
8527 		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);  in bnx2_init_napi()
8528 		bnapi->bp = bp;  in bnx2_init_napi()
8554 	struct bnx2 *bp;  in bnx2_init_one()  local
8562 	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);  in bnx2_init_one()
8574 	bp = netdev_priv(dev);  in bnx2_init_one()
8578 	memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);  in bnx2_init_one()
8584 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_one()
8592 	if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_init_one()
8602 		    ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',  in bnx2_init_one()
8603 		    ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),  in bnx2_init_one()
8604 		    bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),  in bnx2_init_one()
8610 	pci_iounmap(pdev, bp->regview);  in bnx2_init_one()
8623 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_remove_one()  local
8627 	del_timer_sync(&bp->timer);  in bnx2_remove_one()
8628 	cancel_work_sync(&bp->reset_task);  in bnx2_remove_one()
8630 	pci_iounmap(bp->pdev, bp->regview);  in bnx2_remove_one()
8633 	kfree(bp->temp_stats_blk);  in bnx2_remove_one()
8635 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_remove_one()
8637 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_remove_one()
8640 	bnx2_release_firmware(bp);  in bnx2_remove_one()
8654 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_suspend()  local
8657 		cancel_work_sync(&bp->reset_task);  in bnx2_suspend()
8658 		bnx2_netif_stop(bp, true);  in bnx2_suspend()
8660 		del_timer_sync(&bp->timer);  in bnx2_suspend()
8661 		bnx2_shutdown_chip(bp);  in bnx2_suspend()
8662 		__bnx2_free_irq(bp);  in bnx2_suspend()
8663 		bnx2_free_skbs(bp);  in bnx2_suspend()
8665 	bnx2_setup_wol(bp);  in bnx2_suspend()
8674 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_resume()  local
8679 	bnx2_set_power_state(bp, PCI_D0);  in bnx2_resume()
8681 	bnx2_request_irq(bp);  in bnx2_resume()
8682 	bnx2_init_nic(bp, 1);  in bnx2_resume()
8683 	bnx2_netif_start(bp, true);  in bnx2_resume()
8707 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_error_detected()  local
8718 		bnx2_netif_stop(bp, true);  in bnx2_io_error_detected()
8719 		del_timer_sync(&bp->timer);  in bnx2_io_error_detected()
8720 		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_io_error_detected()
8739 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_slot_reset()  local
8753 			err = bnx2_init_nic(bp, 1);  in bnx2_io_slot_reset()
8760 		bnx2_napi_enable(bp);  in bnx2_io_slot_reset()
8765 	if (!(bp->flags & BNX2_FLAG_AER_ENABLED))  in bnx2_io_slot_reset()
8788 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_resume()  local
8792 		bnx2_netif_start(bp, true);  in bnx2_io_resume()
8801 	struct bnx2 *bp;  in bnx2_shutdown()  local
8806 	bp = netdev_priv(dev);  in bnx2_shutdown()
8807 	if (!bp)  in bnx2_shutdown()
8812 		dev_close(bp->dev);  in bnx2_shutdown()
8815 		bnx2_set_power_state(bp, PCI_D3hot);  in bnx2_shutdown()