Lines Matching refs:bp
226 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_en() argument
228 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
231 REG_WR(bp, reg, val); in bnx2x_bits_en()
235 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_dis() argument
237 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
240 REG_WR(bp, reg, val); in bnx2x_bits_dis()
257 struct bnx2x *bp = params->bp; in bnx2x_check_lfa() local
260 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
268 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
275 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
304 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
313 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
322 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
332 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
345 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
355 eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_check_lfa()
374 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) in bnx2x_get_epio() argument
386 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_get_epio()
387 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
389 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; in bnx2x_get_epio()
391 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) in bnx2x_set_epio() argument
403 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); in bnx2x_set_epio()
409 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
412 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_set_epio()
413 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
416 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) in bnx2x_set_cfg_pin() argument
421 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_set_cfg_pin()
425 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); in bnx2x_set_cfg_pin()
429 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) in bnx2x_get_cfg_pin() argument
434 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_get_cfg_pin()
438 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_get_cfg_pin()
449 struct bnx2x *bp = params->bp; in bnx2x_ets_e2e3a0_disabled() local
460 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
480 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
483 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
484 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
487 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
491 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
492 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
494 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
495 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
497 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
540 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_nig() local
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
555 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
563 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
578 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_nig_disabled() local
587 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
588 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
590 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
591 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
596 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
603 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
604 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
620 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
622 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
643 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
647 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
648 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
662 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf() local
681 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
694 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_pbf_disabled() local
707 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
710 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
715 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
720 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
724 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
727 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
741 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
753 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_disabled() local
755 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_disabled()
776 struct bnx2x *bp = params->bp; in bnx2x_ets_disabled() local
779 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) in bnx2x_ets_disabled()
781 else if (CHIP_IS_E3B0(bp)) in bnx2x_ets_disabled()
801 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_cli_map() local
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
811 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
814 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
818 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
830 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, in bnx2x_ets_e3b0_set_cos_bw() argument
891 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
893 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
907 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_get_total_bw() local
967 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_pri_to_cos_set() local
1048 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_set_pri_cli_reg() local
1115 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1118 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1126 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1129 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1142 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_config() local
1155 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_config()
1193 bp, cos_entry, min_w_val_nig, min_w_val_pbf, in bnx2x_ets_e3b0_config()
1243 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit_common() local
1249 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1260 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1264 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1267 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1275 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1278 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1280 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1288 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit() local
1309 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1310 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1312 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1313 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1319 struct bnx2x *bp = params->bp; in bnx2x_ets_strict() local
1330 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1334 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1336 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1338 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1341 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1351 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1363 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_xmac() local
1394 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1395 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1396 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1403 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1404 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1408 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1413 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1423 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, in bnx2x_set_mdio_clk() argument
1431 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_set_mdio_clk()
1433 if (USES_WARPCORE(bp)) in bnx2x_set_mdio_clk()
1449 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1453 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, in bnx2x_set_mdio_emac_per_phy() argument
1460 bnx2x_set_mdio_clk(bp, params->chip_id, in bnx2x_set_mdio_emac_per_phy()
1464 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) in bnx2x_is_4_port_mode() argument
1468 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_is_4_port_mode()
1474 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_is_4_port_mode()
1481 struct bnx2x *bp = params->bp; in bnx2x_emac_init() local
1487 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1495 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1496 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); in bnx2x_emac_init()
1500 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1509 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_emac_init()
1513 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); in bnx2x_emac_init()
1519 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); in bnx2x_emac_init()
1526 struct bnx2x *bp = params->bp; in bnx2x_set_xumac_nig() local
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1532 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1540 struct bnx2x *bp = params->bp; in bnx2x_set_umac_rxtx() local
1541 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_umac_rxtx()
1544 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); in bnx2x_set_umac_rxtx()
1552 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1560 struct bnx2x *bp = params->bp; in bnx2x_umac_enable() local
1562 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1572 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1605 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1615 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1619 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1624 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1641 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1646 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1656 struct bnx2x *bp = params->bp; in bnx2x_xmac_init() local
1657 u32 is_port4mode = bnx2x_is_4_port_mode(bp); in bnx2x_xmac_init()
1665 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || in bnx2x_xmac_init()
1666 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || in bnx2x_xmac_init()
1667 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && in bnx2x_xmac_init()
1669 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_xmac_init()
1677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1693 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1698 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1703 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1707 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1719 struct bnx2x *bp = params->bp; in bnx2x_set_xmac_rxtx() local
1723 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_xmac_rxtx()
1729 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); in bnx2x_set_xmac_rxtx()
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1732 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1735 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); in bnx2x_set_xmac_rxtx()
1740 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1748 struct bnx2x *bp = params->bp; in bnx2x_xmac_enable() local
1762 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1768 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1771 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1772 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1777 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1780 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1787 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1790 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1805 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1817 struct bnx2x *bp = params->bp; in bnx2x_emac_enable() local
1825 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1829 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1839 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1841 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1846 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1849 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1851 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1855 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1858 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1864 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1869 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1874 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1878 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); in bnx2x_emac_enable()
1888 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); in bnx2x_emac_enable()
1892 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, in bnx2x_emac_enable()
1897 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, in bnx2x_emac_enable()
1904 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); in bnx2x_emac_enable()
1907 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_enable()
1912 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); in bnx2x_emac_enable()
1915 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1918 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, in bnx2x_emac_enable()
1923 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1926 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1927 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1928 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1931 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1938 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1939 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1941 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1951 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac1() local
1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1973 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1984 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac2() local
1996 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2007 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2019 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, in bnx2x_update_pfc_bmac2()
2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2043 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, in bnx2x_update_pfc_bmac2()
2058 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2066 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, in bnx2x_pfc_nig_rx_priority_mask() argument
2105 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2111 struct bnx2x *bp = params->bp; in bnx2x_update_mng() local
2113 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2120 struct bnx2x *bp = params->bp; in bnx2x_update_link_attr() local
2122 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_update_link_attr()
2123 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2135 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_nig() local
2146 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2155 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2176 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2177 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2181 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2183 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2186 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2189 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2192 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2196 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2200 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2208 bnx2x_pfc_nig_rx_priority_mask(bp, i, in bnx2x_update_pfc_nig()
2211 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2215 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2219 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2233 struct bnx2x *bp = params->bp; in bnx2x_update_pfc() local
2251 if (CHIP_IS_E3(bp)) { in bnx2x_update_pfc()
2255 val = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_update_pfc()
2263 if (CHIP_IS_E2(bp)) in bnx2x_update_pfc()
2273 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2282 struct bnx2x *bp = params->bp; in bnx2x_bmac1_enable() local
2294 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac1_enable()
2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); in bnx2x_bmac1_enable()
2314 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac1_enable()
2319 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2331 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2336 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac1_enable()
2346 struct bnx2x *bp = params->bp; in bnx2x_bmac2_enable() local
2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac2_enable()
2362 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac2_enable()
2374 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, in bnx2x_bmac2_enable()
2382 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac2_enable()
2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2395 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2400 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2413 struct bnx2x *bp = params->bp; in bnx2x_bmac_enable() local
2417 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2422 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2426 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2429 if (CHIP_IS_E2(bp)) in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2434 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2435 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2441 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2442 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2443 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2444 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2445 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2446 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2452 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) in bnx2x_set_bmac_rx() argument
2457 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); in bnx2x_set_bmac_rx()
2459 if (CHIP_IS_E2(bp)) in bnx2x_set_bmac_rx()
2464 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_bmac_rx()
2468 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2473 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2481 struct bnx2x *bp = params->bp; in bnx2x_pbf_update() local
2487 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2490 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); in bnx2x_pbf_update()
2491 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2496 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2499 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2511 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2513 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2520 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2522 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2534 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2541 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2544 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2563 static u32 bnx2x_get_emac_base(struct bnx2x *bp, in bnx2x_get_emac_base() argument
2571 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2577 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2598 static int bnx2x_cl22_write(struct bnx2x *bp, in bnx2x_cl22_write() argument
2606 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2607 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2614 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2619 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2629 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2633 static int bnx2x_cl22_read(struct bnx2x *bp, in bnx2x_cl22_read() argument
2642 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2643 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2650 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2655 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2668 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2675 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2683 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_read()
2684 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_read()
2685 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2689 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2695 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2700 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2708 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2716 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2721 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2730 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2740 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2745 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2750 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2758 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_write()
2759 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_write()
2760 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2764 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2771 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2776 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2784 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2791 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2796 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2805 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2814 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2818 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2828 struct bnx2x *bp = params->bp; in bnx2x_eee_has_cap() local
2830 if (REG_RD(bp, params->shmem2_base) <= in bnx2x_eee_has_cap()
2880 struct bnx2x *bp = params->bp; in bnx2x_eee_calc_timer() local
2895 eee_mode = ((REG_RD(bp, params->shmem_base + in bnx2x_eee_calc_timer()
2913 struct bnx2x *bp = params->bp; in bnx2x_eee_set_timers() local
2918 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2965 struct bnx2x *bp = params->bp; in bnx2x_eee_disable() local
2968 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2970 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2981 struct bnx2x *bp = params->bp; in bnx2x_eee_advertise() local
2985 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2996 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3006 struct bnx2x *bp = params->bp; in bnx2x_update_mng_eee() local
3009 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3018 struct bnx2x *bp = params->bp; in bnx2x_eee_an_resolve() local
3023 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3024 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3069 struct bnx2x *bp = params->bp; in bnx2x_bsc_module_sel() local
3072 board_cfg = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3080 sfp_ctrl = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3087 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); in bnx2x_bsc_module_sel()
3091 struct bnx2x *bp, in bnx2x_bsc_read() argument
3111 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3113 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3117 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3124 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3128 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3131 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3148 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3152 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3155 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3166 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); in bnx2x_bsc_read()
3177 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3181 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3182 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3185 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, in bnx2x_cl45_read_and_write() argument
3190 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3191 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3203 return bnx2x_cl45_read(params->bp, in bnx2x_phy_read()
3220 return bnx2x_cl45_write(params->bp, in bnx2x_phy_write()
3231 struct bnx2x *bp = params->bp; in bnx2x_get_warpcore_lane() local
3235 path = BP_PATH(bp); in bnx2x_get_warpcore_lane()
3238 if (bnx2x_is_4_port_mode(bp)) { in bnx2x_get_warpcore_lane()
3242 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3246 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3252 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3256 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); in bnx2x_get_warpcore_lane()
3266 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3271 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3286 struct bnx2x *bp = params->bp; in bnx2x_set_aer_mmd() local
3294 if (USES_WARPCORE(bp)) { in bnx2x_set_aer_mmd()
3304 } else if (CHIP_IS_E2(bp)) in bnx2x_set_aer_mmd()
3309 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3318 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) in bnx2x_set_serdes_access() argument
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3326 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3329 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3332 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) in bnx2x_serdes_deassert() argument
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3343 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3345 bnx2x_set_serdes_access(bp, port); in bnx2x_serdes_deassert()
3347 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3355 struct bnx2x *bp = params->bp; in bnx2x_xgxs_specific_func() local
3359 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3360 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3368 struct bnx2x *bp = params->bp; in bnx2x_xgxs_deassert() local
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3379 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
3387 struct bnx2x *bp = params->bp; in bnx2x_calc_ieee_aneg_adv() local
3428 struct bnx2x *bp = params->bp; in set_phy_vars() local
3471 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_set_pause() local
3473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3490 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3498 struct bnx2x *bp = params->bp; in bnx2x_pause_resolve() local
3547 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_update_adv_fc() local
3549 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3550 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3551 } else if (CHIP_IS_E3(bp) && in bnx2x_ext_phy_update_adv_fc()
3555 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3562 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3564 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3567 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3569 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3579 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3582 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3638 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR2() local
3661 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3665 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3677 struct bnx2x *bp = params->bp; in bnx2x_disable_kr2() local
3700 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3711 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_lpi_passthrough() local
3714 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3716 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3724 struct bnx2x *bp = params->bp; in bnx2x_warpcore_restart_AN_KR() local
3726 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3728 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3740 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR() local
3754 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3761 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3772 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3781 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3784 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3792 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3797 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3800 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3803 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3808 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3812 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3818 if (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3822 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3831 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3835 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3842 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3845 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3849 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3858 wc_lane_config = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3861 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3891 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_KR() local
3907 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3912 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3915 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3921 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3929 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3932 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3940 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3944 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3950 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3959 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_XFI() local
3965 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3969 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3973 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3976 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3980 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3984 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3988 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4000 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4010 cfg_tap_val = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_set_10G_XFI()
4056 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4069 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4073 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4079 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4083 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4087 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4095 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_20G_force_KR2() local
4097 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4101 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4106 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4108 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4111 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4119 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4122 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4125 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4135 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4138 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4144 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, in bnx2x_warpcore_set_20G_DXGXS() argument
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4162 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4174 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4177 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4181 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4189 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4193 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4203 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_sgmii_speed() local
4207 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4214 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4219 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4240 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4251 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4258 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4263 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4265 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4275 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4280 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, in bnx2x_warpcore_reset_lane() argument
4286 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4292 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4294 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4302 struct bnx2x *bp = params->bp; in bnx2x_warpcore_clear_regs() local
4321 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4325 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4329 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4334 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, in bnx2x_get_mod_abs_int_cfg() argument
4342 if (CHIP_IS_E3(bp)) { in bnx2x_get_mod_abs_int_cfg()
4343 cfg_pin = (REG_RD(bp, shmem_base + in bnx2x_get_mod_abs_int_cfg()
4376 struct bnx2x *bp = params->bp; in bnx2x_is_sfp_module_plugged() local
4379 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, in bnx2x_is_sfp_module_plugged()
4383 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_is_sfp_module_plugged()
4395 struct bnx2x *bp = params->bp; in bnx2x_warpcore_get_sigdet() local
4399 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4409 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_runtime() local
4420 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_runtime()
4428 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4438 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4439 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4442 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4462 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_sfi() local
4479 struct bnx2x *bp = params->bp; in bnx2x_sfp_e3_set_transmitter() local
4483 cfg_pin = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e3_set_transmitter()
4491 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4493 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4500 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_init() local
4504 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_init()
4512 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4578 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4600 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4607 struct bnx2x *bp = params->bp; in bnx2x_warpcore_link_reset() local
4610 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_warpcore_link_reset()
4613 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4617 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4620 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4624 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4627 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4631 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4635 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4643 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4652 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4662 struct bnx2x *bp = params->bp; in bnx2x_set_warpcore_loopback() local
4673 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4676 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4681 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4694 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4697 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4707 struct bnx2x *bp = params->bp; in bnx2x_sync_link() local
4775 USES_WARPCORE(bp) && in bnx2x_sync_link()
4782 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4787 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4813 struct bnx2x *bp = params->bp; in bnx2x_link_status_update() local
4819 vars->link_status = REG_RD(bp, params->shmem_base + in bnx2x_link_status_update()
4829 vars->eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_link_status_update()
4839 media_types = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4857 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4867 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_link_status_update()
4868 params->link_attr_sync = SHMEM2_RD(bp, in bnx2x_link_status_update()
4880 struct bnx2x *bp = params->bp; in bnx2x_set_master_ln() local
4887 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4892 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4902 struct bnx2x *bp = params->bp; in bnx2x_reset_unicore() local
4905 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4910 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4916 bnx2x_set_serdes_access(bp, params->port); in bnx2x_reset_unicore()
4923 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4934 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_reset_unicore()
4945 struct bnx2x *bp = params->bp; in bnx2x_set_swap_lanes() local
4959 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4966 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4972 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4978 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4987 struct bnx2x *bp = params->bp; in bnx2x_set_parallel_detection() local
4989 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4999 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5009 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5014 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5023 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5029 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5042 struct bnx2x *bp = params->bp; in bnx2x_set_autoneg() local
5046 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5057 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5063 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5074 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5079 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5092 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5099 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5105 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5113 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5124 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5135 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5145 struct bnx2x *bp = params->bp; in bnx2x_program_serdes() local
5149 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5157 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5164 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5184 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5193 struct bnx2x *bp = params->bp; in bnx2x_set_brcm_cl37_advertisement() local
5201 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5214 struct bnx2x *bp = params->bp; in bnx2x_set_ieee_aneg_advertisement() local
5218 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5221 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5226 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5235 struct bnx2x *bp = params->bp; in bnx2x_restart_autoneg() local
5242 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5247 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5255 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5262 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5275 struct bnx2x *bp = params->bp; in bnx2x_initialize_sgmii_process() local
5280 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5289 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5299 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5330 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5346 struct bnx2x *bp = params->bp; in bnx2x_direct_parallel_detect_used() local
5350 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5354 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5364 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5385 struct bnx2x *bp = params->bp; in bnx2x_update_adv_fc() local
5392 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5396 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5406 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5410 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5429 struct bnx2x *bp = params->bp; in bnx2x_flow_ctrl_resolve() local
5455 struct bnx2x *bp = params->bp; in bnx2x_check_fallback_to_cl37() local
5459 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5467 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5474 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5490 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5511 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5540 struct bnx2x *bp = params->bp; in bnx2x_get_link_speed_duplex() local
5628 struct bnx2x *bp = params->bp; in bnx2x_link_settings_status() local
5634 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5671 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5682 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5702 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_status() local
5710 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5712 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5720 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5728 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5739 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5741 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5773 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5784 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5798 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5801 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5825 struct bnx2x *bp = params->bp; in bnx2x_set_gmii_tx_driver() local
5832 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5846 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5855 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5865 struct bnx2x *bp = params->bp; in bnx2x_emac_program() local
5870 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + in bnx2x_emac_program()
5901 bnx2x_bits_en(bp, in bnx2x_emac_program()
5914 struct bnx2x *bp = params->bp; in bnx2x_set_preemphasis() local
5918 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5926 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5937 struct bnx2x *bp = params->bp; in bnx2x_xgxs_config_init() local
6021 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, in bnx2x_wait_reset_complete() argument
6029 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
6032 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
6041 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_wait_reset_complete()
6052 struct bnx2x *bp = params->bp; in bnx2x_link_int_enable() local
6055 if (CHIP_IS_E3(bp)) { in bnx2x_link_int_enable()
6080 bnx2x_bits_en(bp, in bnx2x_link_int_enable()
6086 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_int_enable()
6088 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_int_enable()
6089 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), in bnx2x_link_int_enable()
6090 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); in bnx2x_link_int_enable()
6092 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_int_enable()
6093 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_int_enable()
6096 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, in bnx2x_rearm_latch_signal() argument
6106 latch_status = REG_RD(bp, in bnx2x_rearm_latch_signal()
6111 bnx2x_bits_en(bp, in bnx2x_rearm_latch_signal()
6116 bnx2x_bits_dis(bp, in bnx2x_rearm_latch_signal()
6124 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6133 struct bnx2x *bp = params->bp; in bnx2x_link_int_ack() local
6139 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, in bnx2x_link_int_ack()
6144 if (USES_WARPCORE(bp)) in bnx2x_link_int_ack()
6164 bnx2x_bits_en(bp, in bnx2x_link_int_ack()
6219 struct bnx2x *bp; in bnx2x_get_ext_phy_fw_version() local
6226 bp = params->bp; in bnx2x_get_ext_phy_fw_version()
6230 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6240 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6260 struct bnx2x *bp = params->bp; in bnx2x_set_xgxs_loopback() local
6267 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6269 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + in bnx2x_set_xgxs_loopback()
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6276 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6282 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6291 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6293 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6299 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6303 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6320 struct bnx2x *bp = params->bp; in bnx2x_set_led() local
6335 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6336 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6339 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6348 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); in bnx2x_set_led()
6362 CHIP_IS_E2(bp) && params->num_phys == 2) { in bnx2x_set_led()
6366 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6367 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6369 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6370 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6384 if ((!CHIP_IS_E3(bp)) || in bnx2x_set_led()
6385 (CHIP_IS_E3(bp) && in bnx2x_set_led()
6387 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6389 if (CHIP_IS_E1x(bp) || in bnx2x_set_led()
6390 CHIP_IS_E2(bp) || in bnx2x_set_led()
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6394 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6399 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6400 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6401 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | in bnx2x_set_led()
6413 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6417 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6419 if (CHIP_IS_E3(bp)) in bnx2x_set_led()
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6423 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6425 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6427 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6428 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6431 if (CHIP_IS_E1(bp) && in bnx2x_set_led()
6437 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6439 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6441 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6462 struct bnx2x *bp = params->bp; in bnx2x_test_link() local
6468 if (CHIP_IS_E3(bp)) { in bnx2x_test_link()
6473 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6475 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6481 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6491 CL22_RD_OVER_CL45(bp, int_phy, in bnx2x_test_link()
6544 struct bnx2x *bp = params->bp; in bnx2x_link_initialize() local
6556 if (!USES_WARPCORE(bp)) in bnx2x_link_initialize()
6567 (CHIP_IS_E1x(bp) || in bnx2x_link_initialize()
6568 CHIP_IS_E2(bp))) in bnx2x_link_initialize()
6609 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + in bnx2x_link_initialize()
6622 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6629 struct bnx2x *bp = params->bp; in bnx2x_common_ext_link_reset() local
6632 if (CHIP_IS_E2(bp)) in bnx2x_common_ext_link_reset()
6633 gpio_port = BP_PATH(bp); in bnx2x_common_ext_link_reset()
6636 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_common_ext_link_reset()
6639 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_common_ext_link_reset()
6648 struct bnx2x *bp = params->bp; in bnx2x_update_link_down() local
6663 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6666 if (!CHIP_IS_E3(bp)) in bnx2x_update_link_down()
6667 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6671 if (CHIP_IS_E1x(bp) || in bnx2x_update_link_down()
6672 CHIP_IS_E2(bp)) in bnx2x_update_link_down()
6673 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_update_link_down()
6675 if (CHIP_IS_E3(bp)) { in bnx2x_update_link_down()
6677 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6679 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6696 struct bnx2x *bp = params->bp; in bnx2x_update_link_up() local
6711 if (USES_WARPCORE(bp)) { in bnx2x_update_link_up()
6728 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6730 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6731 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6735 if ((CHIP_IS_E1x(bp) || in bnx2x_update_link_up()
6736 CHIP_IS_E2(bp))) { in bnx2x_update_link_up()
6762 if (CHIP_IS_E1x(bp)) in bnx2x_update_link_up()
6767 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6785 struct bnx2x *bp = params->bp; in bnx2x_chng_link_count() local
6789 if (!(SHMEM2_HAS(bp, link_change_count))) in bnx2x_chng_link_count()
6797 val = REG_RD(bp, addr) + 1; in bnx2x_chng_link_count()
6798 REG_WR(bp, addr, val); in bnx2x_chng_link_count()
6815 struct bnx2x *bp = params->bp; in bnx2x_link_update() local
6840 if (USES_WARPCORE(bp)) in bnx2x_link_update()
6845 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_update()
6847 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + in bnx2x_link_update()
6850 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_update()
6852 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); in bnx2x_link_update()
6855 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_update()
6856 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_update()
6859 if (!CHIP_IS_E3(bp)) in bnx2x_link_update()
6860 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6978 bnx2x_rearm_latch_signal(bp, port, in bnx2x_link_update()
7001 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
7064 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); in bnx2x_link_update()
7072 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) in bnx2x_ext_phy_hw_reset() argument
7074 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7077 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7081 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, in bnx2x_save_spirom_version() argument
7088 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
7091 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, in bnx2x_save_bcm_spirom_ver() argument
7097 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7099 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7101 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), in bnx2x_save_bcm_spirom_ver()
7105 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, in bnx2x_ext_phy_10G_an_resolve() argument
7110 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7113 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7129 struct bnx2x *bp = params->bp; in bnx2x_8073_resolve_fc() local
7141 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7145 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7158 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, in bnx2x_8073_8727_external_rom_boot() argument
7168 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7174 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7179 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7184 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7190 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7210 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7213 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7223 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7226 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7239 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7245 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7254 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7265 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7269 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7284 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7303 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7321 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7324 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7326 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7328 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7330 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7339 struct bnx2x *bp = params->bp; in bnx2x_8073_set_pause_cl37() local
7340 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7364 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7373 struct bnx2x *bp = params->bp; in bnx2x_8073_specific_func() local
7377 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7379 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7389 struct bnx2x *bp = params->bp; in bnx2x_8073_config_init() local
7394 if (CHIP_IS_E2(bp)) in bnx2x_8073_config_init()
7395 gpio_port = BP_PATH(bp); in bnx2x_8073_config_init()
7399 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_config_init()
7402 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8073_config_init()
7408 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7411 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7421 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7424 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7432 if (REG_RD(bp, params->shmem_base + in bnx2x_8073_config_init()
7437 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7440 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7446 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7450 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7478 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7485 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7498 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7502 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7507 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7513 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7514 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7519 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7521 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7527 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7537 struct bnx2x *bp = params->bp; in bnx2x_8073_read_status() local
7543 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7549 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7551 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7555 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7559 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7565 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7569 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7571 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7578 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7581 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7583 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7587 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7589 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7595 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7600 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7605 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7609 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7640 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7653 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7658 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7664 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7681 struct bnx2x *bp = params->bp; in bnx2x_8073_link_reset() local
7683 if (CHIP_IS_E2(bp)) in bnx2x_8073_link_reset()
7684 gpio_port = BP_PATH(bp); in bnx2x_8073_link_reset()
7689 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_link_reset()
7701 struct bnx2x *bp = params->bp; in bnx2x_8705_config_init() local
7704 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8705_config_init()
7707 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8705_config_init()
7708 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7709 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7711 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7713 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7715 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7717 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7720 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); in bnx2x_8705_config_init()
7730 struct bnx2x *bp = params->bp; in bnx2x_8705_read_status() local
7732 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7736 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7740 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7743 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7745 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7764 struct bnx2x *bp = params->bp; in bnx2x_set_disable_pmd_transmit() local
7778 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7787 struct bnx2x *bp = params->bp; in bnx2x_get_gpio_port() local
7788 if (CHIP_IS_E2(bp)) in bnx2x_get_gpio_port()
7789 gpio_port = BP_PATH(bp); in bnx2x_get_gpio_port()
7792 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_get_gpio_port()
7793 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_get_gpio_port()
7803 struct bnx2x *bp = params->bp; in bnx2x_sfp_e1e2_set_transmitter() local
7807 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e1e2_set_transmitter()
7816 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7826 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7845 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_sfp_e1e2_set_transmitter()
7858 struct bnx2x *bp = params->bp; in bnx2x_sfp_set_transmitter() local
7860 if (CHIP_IS_E3(bp)) in bnx2x_sfp_set_transmitter()
7871 struct bnx2x *bp = params->bp; in bnx2x_8726_read_sfp_module_eeprom() local
7880 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7885 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7890 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7896 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7915 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7922 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7937 struct bnx2x *bp = params->bp; in bnx2x_warpcore_power_module() local
7939 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_power_module()
7952 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); in bnx2x_warpcore_power_module()
7964 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_sfp_module_eeprom() local
7981 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, in bnx2x_warpcore_read_sfp_module_eeprom()
8000 struct bnx2x *bp = params->bp; in bnx2x_8727_read_sfp_module_eeprom() local
8013 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8019 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8025 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8031 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8036 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8042 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8053 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8072 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8079 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8095 struct bnx2x *bp = params->bp; in bnx2x_read_sfp_module_eeprom() local
8136 struct bnx2x *bp = params->bp; in bnx2x_get_edc_mode() local
8203 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_edc_mode()
8204 gport = BP_PATH(bp) + in bnx2x_get_edc_mode()
8207 netdev_err(bp->dev, in bnx2x_get_edc_mode()
8238 media_types = REG_RD(bp, sync_offset); in bnx2x_get_edc_mode()
8250 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8277 struct bnx2x *bp = params->bp; in bnx2x_verify_sfp_module() local
8283 val = REG_RD(bp, params->shmem_base + in bnx2x_verify_sfp_module()
8313 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); in bnx2x_verify_sfp_module()
8339 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," in bnx2x_verify_sfp_module()
8354 struct bnx2x *bp = params->bp; in bnx2x_wait_for_sfp_module_initialized() local
8382 static void bnx2x_8727_power_module(struct bnx2x *bp, in bnx2x_8727_power_module() argument
8408 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8414 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, in bnx2x_8726_set_limiting_mode() argument
8420 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8429 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8443 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8447 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8451 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8455 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8463 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, in bnx2x_8727_set_limiting_mode() argument
8469 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8474 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8479 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8484 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8489 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8501 struct bnx2x *bp = params->bp; in bnx2x_8727_specific_func() local
8512 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8515 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8518 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8521 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8532 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8546 struct bnx2x *bp = params->bp; in bnx2x_set_e1e2_module_fault_led() local
8548 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + in bnx2x_set_e1e2_module_fault_led()
8566 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_set_e1e2_module_fault_led()
8580 struct bnx2x *bp = params->bp; in bnx2x_set_e3_module_fault_led() local
8581 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_set_e3_module_fault_led()
8588 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); in bnx2x_set_e3_module_fault_led()
8594 struct bnx2x *bp = params->bp; in bnx2x_set_sfp_module_fault_led() local
8596 if (CHIP_IS_E3(bp)) { in bnx2x_set_sfp_module_fault_led()
8608 struct bnx2x *bp = params->bp; in bnx2x_warpcore_hw_reset() local
8611 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8614 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8615 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8616 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
8623 struct bnx2x *bp = params->bp; in bnx2x_power_sfp_module() local
8629 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8644 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_limiting_mode() local
8648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8666 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8669 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8673 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8674 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8684 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8688 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8699 struct bnx2x *bp = params->bp; in bnx2x_sfp_module_detection() local
8703 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_sfp_module_detection()
8753 struct bnx2x *bp = params->bp; in bnx2x_handle_module_detect_int() local
8757 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8764 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, in bnx2x_handle_module_detect_int()
8775 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_handle_module_detect_int()
8779 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_handle_module_detect_int()
8783 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8788 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8794 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8801 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8803 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8810 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8823 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, in bnx2x_sfp_mask_fault() argument
8829 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8832 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8836 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8841 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8852 struct bnx2x *bp = params->bp; in bnx2x_8706_8726_read_status() local
8855 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8858 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8862 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8864 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8868 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8870 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8872 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8874 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8894 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8896 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8914 struct bnx2x *bp = params->bp; in bnx2x_8706_config_init() local
8916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8706_config_init()
8919 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8706_config_init()
8920 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8921 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8925 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8940 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8947 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8954 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8957 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8961 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8968 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8972 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8975 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8978 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8982 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8984 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8987 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8991 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8997 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8706_config_init()
9004 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
9007 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
9027 struct bnx2x *bp = params->bp; in bnx2x_8726_config_loopback() local
9029 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
9035 struct bnx2x *bp = params->bp; in bnx2x_8726_external_rom_boot() local
9040 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9044 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9049 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9053 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9062 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9067 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9074 struct bnx2x *bp = params->bp; in bnx2x_8726_read_status() local
9078 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
9095 struct bnx2x *bp = params->bp; in bnx2x_8726_config_init() local
9098 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9099 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9112 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9114 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9116 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9118 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9130 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9132 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9134 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9136 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9138 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9143 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9145 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9150 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9161 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9166 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9179 struct bnx2x *bp = params->bp; in bnx2x_8726_link_reset() local
9182 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9194 struct bnx2x *bp = params->bp; in bnx2x_8727_set_link_led() local
9216 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9222 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9226 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9232 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9244 struct bnx2x *bp = params->bp; in bnx2x_8727_hw_reset() local
9245 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_hw_reset()
9246 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_hw_reset()
9248 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8727_hw_reset()
9255 struct bnx2x *bp = params->bp; in bnx2x_8727_config_speed() local
9261 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9263 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9265 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9272 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9276 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9288 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9290 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9296 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9299 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9301 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9303 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9315 struct bnx2x *bp = params->bp; in bnx2x_8727_config_init() local
9318 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9326 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9335 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9341 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9343 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9346 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9358 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9362 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9370 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8727_config_init()
9378 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9382 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9384 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9387 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9398 struct bnx2x *bp = params->bp; in bnx2x_8727_handle_mod_abs() local
9400 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_8727_handle_mod_abs()
9404 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9423 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9430 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9448 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9457 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9485 struct bnx2x *bp = params->bp; in bnx2x_8727_read_status() local
9491 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9498 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9504 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9507 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9513 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9521 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9526 if (!CHIP_IS_E1x(bp)) in bnx2x_8727_read_status()
9527 oc_port = BP_PATH(bp) + (params->port << 1); in bnx2x_8727_read_status()
9531 netdev_err(bp->dev, "Error: Power fault on Port %d has " in bnx2x_8727_read_status()
9540 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9544 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9549 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9553 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9556 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9565 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9578 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9603 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9606 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9622 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9632 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9642 struct bnx2x *bp = params->bp; in bnx2x_8727_link_reset() local
9650 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9665 struct bnx2x *bp, in bnx2x_save_848xx_spirom_version() argument
9679 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9680 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, in bnx2x_save_848xx_spirom_version()
9686 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9690 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9698 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9705 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9706 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9707 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9709 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9717 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9723 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9725 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9727 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, in bnx2x_save_848xx_spirom_version()
9732 static void bnx2x_848xx_set_led(struct bnx2x *bp, in bnx2x_848xx_set_led() argument
9746 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9752 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9757 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9766 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9775 struct bnx2x *bp = params->bp; in bnx2x_848xx_specific_func() local
9780 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9786 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, in bnx2x_848xx_specific_func()
9789 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9798 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmn_config_init() local
9802 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9806 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9811 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9815 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9834 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9882 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9894 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9900 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9912 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9924 bp, phy, in bnx2x_848xx_cmn_config_init()
9928 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9932 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9944 struct bnx2x *bp = params->bp; in bnx2x_8481_config_init() local
9946 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8481_config_init()
9950 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8481_config_init()
9951 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9953 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9967 struct bnx2x *bp = params->bp; in bnx2x_84858_cmd_hdlr() local
9977 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
9994 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10002 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10011 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10029 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10043 struct bnx2x *bp = params->bp; in bnx2x_84833_cmd_hdlr() local
10045 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10049 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10062 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10066 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10069 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10083 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10087 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10098 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmd_hdlr() local
10101 (REG_RD(bp, params->shmem2_base + in bnx2x_848xx_cmd_hdlr()
10120 struct bnx2x *bp = params->bp; in bnx2x_848xx_pair_swap_cfg() local
10123 pair_swap = REG_RD(bp, params->shmem_base + in bnx2x_848xx_pair_swap_cfg()
10143 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, in bnx2x_84833_get_reset_gpios() argument
10150 if (CHIP_IS_E3(bp)) { in bnx2x_84833_get_reset_gpios()
10154 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
10167 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
10184 struct bnx2x *bp = params->bp; in bnx2x_84833_hw_reset_phy() local
10186 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + in bnx2x_84833_hw_reset_phy()
10193 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10196 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10203 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, in bnx2x_84833_hw_reset_phy()
10206 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_hw_reset_phy()
10219 struct bnx2x *bp = params->bp; in bnx2x_8483x_disable_eee() local
10240 struct bnx2x *bp = params->bp; in bnx2x_8483x_enable_eee() local
10258 struct bnx2x *bp = params->bp; in bnx2x_848x3_config_init() local
10267 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_config_init()
10268 port = BP_PATH(bp); in bnx2x_848x3_config_init()
10273 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_config_init()
10278 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10283 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10302 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848x3_config_init()
10311 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10319 if (CHIP_IS_E3(bp)) { in bnx2x_848x3_config_init()
10350 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10372 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10375 u32 cms_enable = REG_RD(bp, params->shmem_base + in bnx2x_848x3_config_init()
10380 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10386 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10390 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10421 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10433 struct bnx2x *bp = params->bp; in bnx2x_848xx_read_status() local
10440 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10442 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10452 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10457 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10462 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10493 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10500 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10515 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10533 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10543 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10570 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10572 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10579 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10581 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10588 struct bnx2x *bp = params->bp; in bnx2x_848x3_link_reset() local
10592 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_link_reset()
10593 port = BP_PATH(bp); in bnx2x_848x3_link_reset()
10598 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_link_reset()
10602 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10606 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10615 struct bnx2x *bp = params->bp; in bnx2x_848xx_set_link_led() local
10619 if (!(CHIP_IS_E1x(bp))) in bnx2x_848xx_set_link_led()
10620 port = BP_PATH(bp); in bnx2x_848xx_set_link_led()
10633 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10638 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10643 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10648 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10654 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10669 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10674 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10679 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10684 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10690 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10699 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10706 bp, in bnx2x_848xx_set_link_led()
10711 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10725 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10732 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10738 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10743 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10748 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10753 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10758 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10767 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10774 bp, in bnx2x_848xx_set_link_led()
10779 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10795 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10804 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10811 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10816 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10821 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10826 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10840 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10846 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10852 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10861 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10879 if (CHIP_IS_E3(bp)) { in bnx2x_848xx_set_link_led()
10880 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10892 struct bnx2x *bp = params->bp; in bnx2x_54618se_specific_func() local
10898 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10901 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10906 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10910 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10921 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_init() local
10934 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_config_init()
10941 bnx2x_set_cfg_pin(bp, cfg_pin, 1); in bnx2x_54618se_config_init()
10947 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10949 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10957 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10960 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10964 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10981 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10985 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10989 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
11010 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11013 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
11049 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11056 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11065 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
11068 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
11070 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
11105 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
11110 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11117 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11127 struct bnx2x *bp = params->bp; in bnx2x_5461x_set_link_led() local
11130 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11133 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
11153 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11163 struct bnx2x *bp = params->bp; in bnx2x_54618se_link_reset() local
11170 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
11175 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_link_reset()
11182 bnx2x_set_cfg_pin(bp, cfg_pin, 0); in bnx2x_54618se_link_reset()
11189 struct bnx2x *bp = params->bp; in bnx2x_54618se_read_status() local
11195 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11201 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11238 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11244 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11258 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11276 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11295 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_loopback() local
11303 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11310 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11313 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11319 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11320 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11321 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11324 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11329 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
11338 struct bnx2x *bp = params->bp; in bnx2x_7101_config_loopback() local
11340 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11349 struct bnx2x *bp = params->bp; in bnx2x_7101_config_init() local
11353 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_config_init()
11356 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_7101_config_init()
11357 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11359 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11362 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11367 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11370 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11374 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11377 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11379 bnx2x_save_spirom_version(bp, params->port, in bnx2x_7101_config_init()
11388 struct bnx2x *bp = params->bp; in bnx2x_7101_read_status() local
11391 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11393 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11397 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11399 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11406 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11413 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11437 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11441 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11448 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11453 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11465 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_hw_reset()
11468 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_7101_hw_reset()
11476 struct bnx2x *bp = params->bp; in bnx2x_7101_set_link_led() local
11489 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
12030 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, in bnx2x_populate_preemphasis() argument
12042 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
12046 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
12050 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
12054 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
12067 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_config() argument
12073 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
12078 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
12089 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, in bnx2x_populate_int_phy() argument
12094 u32 switch_cfg = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
12098 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_populate_int_phy()
12099 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_populate_int_phy()
12102 if (USES_WARPCORE(bp)) { in bnx2x_populate_int_phy()
12104 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
12107 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) in bnx2x_populate_int_phy()
12112 serdes_net_if = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
12187 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_populate_int_phy()
12194 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
12200 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
12211 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
12214 if (CHIP_IS_E2(bp)) in bnx2x_populate_int_phy()
12222 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
12226 static int bnx2x_populate_ext_phy(struct bnx2x *bp, in bnx2x_populate_ext_phy() argument
12235 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, in bnx2x_populate_ext_phy()
12302 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12308 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12319 u32 size = REG_RD(bp, shmem2_base); in bnx2x_populate_ext_phy()
12334 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12340 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12354 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, in bnx2x_populate_phy() argument
12360 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12361 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_populate_phy()
12370 struct bnx2x *bp = params->bp; in bnx2x_phy_def_cfg() local
12374 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12377 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12382 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12385 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12475 struct bnx2x *bp = params->bp; in bnx2x_phy_probe() local
12495 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, in bnx2x_phy_probe()
12521 media_types = REG_RD(bp, sync_offset); in bnx2x_phy_probe()
12535 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12548 struct bnx2x *bp = params->bp; in bnx2x_init_bmac_loopback() local
12562 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_bmac_loopback()
12568 struct bnx2x *bp = params->bp; in bnx2x_init_emac_loopback() local
12581 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_emac_loopback()
12587 struct bnx2x *bp = params->bp; in bnx2x_init_xmac_loopback() local
12601 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12607 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12613 struct bnx2x *bp = params->bp; in bnx2x_init_umac_loopback() local
12622 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12628 struct bnx2x *bp = params->bp; in bnx2x_init_xgxs_loopback() local
12641 if (!USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12646 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12653 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12672 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12679 struct bnx2x *bp = params->bp; in bnx2x_set_rx_filter() local
12683 if (!CHIP_IS_E1x(bp)) in bnx2x_set_rx_filter()
12685 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12687 if (!CHIP_IS_E1(bp)) { in bnx2x_set_rx_filter()
12688 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12692 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12700 struct bnx2x *bp = params->bp; in bnx2x_avoid_link_flap() local
12702 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_avoid_link_flap()
12722 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12729 if (CHIP_IS_E3(bp)) { in bnx2x_avoid_link_flap()
12731 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12735 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12759 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12763 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12775 struct bnx2x *bp = params->bp; in bnx2x_cannot_avoid_link_flap() local
12782 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12786 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12790 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12795 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12801 tmp_val = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12806 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12809 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12825 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12833 struct bnx2x *bp = params->bp; in bnx2x_phy_init() local
12866 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_phy_init()
12902 if (!CHIP_IS_E3(bp)) { in bnx2x_phy_init()
12906 bnx2x_serdes_deassert(bp, params->port); in bnx2x_phy_init()
12922 struct bnx2x *bp = params->bp; in bnx2x_link_reset() local
12932 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, in bnx2x_link_reset()
12939 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
12942 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12943 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12944 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12947 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12948 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); in bnx2x_link_reset()
12954 if (!CHIP_IS_E3(bp)) in bnx2x_link_reset()
12955 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
12962 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_link_reset()
12983 bnx2x_rearm_latch_signal(bp, port, 0); in bnx2x_link_reset()
12984 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, in bnx2x_link_reset()
12992 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12994 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
12996 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12997 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13001 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_link_reset()
13003 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
13013 struct bnx2x *bp = params->bp; in bnx2x_lfa_reset() local
13023 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
13029 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
13030 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_lfa_reset()
13032 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
13050 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
13051 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); in bnx2x_lfa_reset()
13053 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
13058 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13065 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, in bnx2x_8073_common_init_phy() argument
13076 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8073_common_init_phy()
13077 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8073_common_init_phy()
13079 bnx2x_ext_phy_hw_reset(bp, port); in bnx2x_8073_common_init_phy()
13084 if (CHIP_IS_E1x(bp)) { in bnx2x_8073_common_init_phy()
13095 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8073_common_init_phy()
13102 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8073_common_init_phy()
13112 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
13117 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
13136 if (CHIP_IS_E1x(bp)) in bnx2x_8073_common_init_phy()
13143 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13148 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13153 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13168 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13172 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13178 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13181 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13186 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
13191 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, in bnx2x_8726_common_init_phy() argument
13201 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_8726_common_init_phy()
13204 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
13206 bnx2x_ext_phy_hw_reset(bp, 0); in bnx2x_8726_common_init_phy()
13212 if (CHIP_IS_E1x(bp)) { in bnx2x_8726_common_init_phy()
13220 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8726_common_init_phy()
13228 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13233 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, in bnx2x_8726_common_init_phy()
13240 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_reset_gpio() argument
13244 u32 phy_gpio_reset = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_reset_gpio()
13286 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, in bnx2x_8727_common_init_phy() argument
13296 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_common_init_phy()
13297 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_common_init_phy()
13305 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], in bnx2x_8727_common_init_phy()
13312 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, in bnx2x_8727_common_init_phy()
13315 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, in bnx2x_8727_common_init_phy()
13325 if (CHIP_IS_E1x(bp)) { in bnx2x_8727_common_init_phy()
13336 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8727_common_init_phy()
13343 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8727_common_init_phy()
13352 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13367 if (CHIP_IS_E1x(bp)) in bnx2x_8727_common_init_phy()
13373 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13377 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13385 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, in bnx2x_84833_common_init_phy() argument
13392 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); in bnx2x_84833_common_init_phy()
13393 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_common_init_phy()
13395 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); in bnx2x_84833_common_init_phy()
13401 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_ext_phy_common_init() argument
13409 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13416 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13425 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13435 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13450 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_ext_phy_common_init()
13456 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_common_init_phy() argument
13464 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); in bnx2x_common_init_phy()
13465 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); in bnx2x_common_init_phy()
13467 if (CHIP_IS_E3(bp)) { in bnx2x_common_init_phy()
13469 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); in bnx2x_common_init_phy()
13470 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13473 phy_ver = REG_RD(bp, shmem_base_path[0] + in bnx2x_common_init_phy()
13485 ext_phy_config = bnx2x_get_ext_phy_config(bp, in bnx2x_common_init_phy()
13489 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, in bnx2x_common_init_phy()
13500 struct bnx2x *bp = params->bp; in bnx2x_check_over_curr() local
13505 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_check_over_curr()
13512 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) in bnx2x_check_over_curr()
13517 netdev_err(bp->dev, "Error: Power fault on Port %d has" in bnx2x_check_over_curr()
13537 struct bnx2x *bp = params->bp; in bnx2x_analyze_link_error() local
13573 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13586 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13598 bnx2x_notify_link_changed(bp); in bnx2x_analyze_link_error()
13616 struct bnx2x *bp = params->bp; in bnx2x_check_half_open_conn() local
13621 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) in bnx2x_check_half_open_conn()
13624 if (CHIP_IS_E3(bp) && in bnx2x_check_half_open_conn()
13625 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13635 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13636 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13639 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13645 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13653 if (CHIP_IS_E2(bp)) in bnx2x_check_half_open_conn()
13658 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()
13671 struct bnx2x *bp = params->bp; in bnx2x_sfp_tx_fault_detection() local
13676 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, in bnx2x_sfp_tx_fault_detection()
13681 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { in bnx2x_sfp_tx_fault_detection()
13714 struct bnx2x *bp = params->bp; in bnx2x_kr2_recovery() local
13724 struct bnx2x *bp = params->bp; in bnx2x_check_kr2_wa() local
13748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13750 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13752 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13796 struct bnx2x *bp = params->bp; in bnx2x_period_func() local
13807 if (CHIP_IS_E3(bp)) { in bnx2x_period_func()
13817 if ((REG_RD(bp, params->shmem_base + in bnx2x_period_func()
13836 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, in bnx2x_fan_failure_det_req() argument
13845 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_fan_failure_det_req()
13860 struct bnx2x *bp = params->bp; in bnx2x_hw_reset_phy() local
13862 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_hw_reset_phy()
13879 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, in bnx2x_init_mod_abs_int() argument
13886 if (CHIP_IS_E3(bp)) { in bnx2x_init_mod_abs_int()
13887 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, in bnx2x_init_mod_abs_int()
13897 if (bnx2x_populate_phy(bp, phy_index, shmem_base, in bnx2x_init_mod_abs_int()
13915 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); in bnx2x_init_mod_abs_int()
13917 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_init_mod_abs_int()
13918 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_init_mod_abs_int()
13927 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
13938 aeu_mask = REG_RD(bp, offset); in bnx2x_init_mod_abs_int()
13940 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
13943 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_init_mod_abs_int()
13945 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()