Lines Matching refs:bp
293 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
299 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
301 static void __storm_memset_dma_mapping(struct bnx2x *bp, in __storm_memset_dma_mapping() argument
304 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
305 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
308 static void storm_memset_spq_addr(struct bnx2x *bp, in storm_memset_spq_addr() argument
314 __storm_memset_dma_mapping(bp, addr, mapping); in storm_memset_spq_addr()
317 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, in storm_memset_vf_to_pf() argument
320 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
322 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
324 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
326 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
330 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, in storm_memset_func_en() argument
333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
343 static void storm_memset_eq_data(struct bnx2x *bp, in storm_memset_eq_data() argument
351 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); in storm_memset_eq_data()
354 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, in storm_memset_eq_prod() argument
358 REG_WR16(bp, addr, eq_prod); in storm_memset_eq_prod()
364 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) in bnx2x_reg_wr_ind() argument
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_wr_ind()
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); in bnx2x_reg_wr_ind()
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_wr_ind()
372 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) in bnx2x_reg_rd_ind() argument
376 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_rd_ind()
377 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); in bnx2x_reg_rd_ind()
378 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_rd_ind()
390 static void bnx2x_dp_dmae(struct bnx2x *bp, in bnx2x_dp_dmae() argument
457 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) in bnx2x_post_dmae() argument
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
466 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
480 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, in bnx2x_dmae_opcode() argument
490 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); in bnx2x_dmae_opcode()
491 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | in bnx2x_dmae_opcode()
492 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); in bnx2x_dmae_opcode()
505 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, in bnx2x_prep_dmae_with_comp() argument
512 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, in bnx2x_prep_dmae_with_comp()
516 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
517 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
522 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, in bnx2x_issue_dmae_with_comp() argument
525 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; in bnx2x_issue_dmae_with_comp()
528 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); in bnx2x_issue_dmae_with_comp()
535 spin_lock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
541 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); in bnx2x_issue_dmae_with_comp()
548 (bp->recovery_state != BNX2X_RECOVERY_DONE && in bnx2x_issue_dmae_with_comp()
549 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_issue_dmae_with_comp()
564 spin_unlock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
569 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, in bnx2x_write_dmae() argument
575 if (!bp->dmae_ready) { in bnx2x_write_dmae()
576 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_write_dmae()
578 if (CHIP_IS_E1(bp)) in bnx2x_write_dmae()
579 bnx2x_init_ind_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
581 bnx2x_init_str_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
586 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); in bnx2x_write_dmae()
596 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_write_dmae()
605 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) in bnx2x_read_dmae() argument
610 if (!bp->dmae_ready) { in bnx2x_read_dmae()
611 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_read_dmae()
614 if (CHIP_IS_E1(bp)) in bnx2x_read_dmae()
616 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); in bnx2x_read_dmae()
619 data[i] = REG_RD(bp, src_addr + i*4); in bnx2x_read_dmae()
625 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); in bnx2x_read_dmae()
630 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
631 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
635 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_read_dmae()
644 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, in bnx2x_write_dmae_phys_len() argument
647 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); in bnx2x_write_dmae_phys_len()
651 bnx2x_write_dmae(bp, phys_addr + offset, in bnx2x_write_dmae_phys_len()
657 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); in bnx2x_write_dmae_phys_len()
671 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, in bnx2x_get_assert_list_entry() argument
691 static int bnx2x_mc_assert(struct bnx2x *bp) in bnx2x_mc_assert() argument
717 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
727 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
728 bnx2x_get_assert_list_entry(bp, in bnx2x_mc_assert()
746 CHIP_IS_E1(bp) ? "everest1" : in bnx2x_mc_assert()
747 CHIP_IS_E1H(bp) ? "everest1h" : in bnx2x_mc_assert()
748 CHIP_IS_E2(bp) ? "everest2" : "everest3", in bnx2x_mc_assert()
757 #define SCRATCH_BUFFER_SIZE(bp) \ argument
758 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
760 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) in bnx2x_fw_dump_lvl() argument
767 if (BP_NOMCP(bp)) { in bnx2x_fw_dump_lvl()
771 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", in bnx2x_fw_dump_lvl()
772 (bp->common.bc_ver & 0xff0000) >> 16, in bnx2x_fw_dump_lvl()
773 (bp->common.bc_ver & 0xff00) >> 8, in bnx2x_fw_dump_lvl()
774 (bp->common.bc_ver & 0xff)); in bnx2x_fw_dump_lvl()
776 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); in bnx2x_fw_dump_lvl()
777 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) in bnx2x_fw_dump_lvl()
780 if (BP_PATH(bp) == 0) in bnx2x_fw_dump_lvl()
781 trace_shmem_base = bp->common.shmem_base; in bnx2x_fw_dump_lvl()
783 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x_fw_dump_lvl()
786 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || in bnx2x_fw_dump_lvl()
787 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + in bnx2x_fw_dump_lvl()
788 SCRATCH_BUFFER_SIZE(bp)) { in bnx2x_fw_dump_lvl()
797 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
805 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
806 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; in bnx2x_fw_dump_lvl()
818 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
826 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
833 static void bnx2x_fw_dump(struct bnx2x *bp) in bnx2x_fw_dump() argument
835 bnx2x_fw_dump_lvl(bp, KERN_ERR); in bnx2x_fw_dump()
838 static void bnx2x_hc_int_disable(struct bnx2x *bp) in bnx2x_hc_int_disable() argument
840 int port = BP_PORT(bp); in bnx2x_hc_int_disable()
842 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_disable()
848 if (CHIP_IS_E1(bp)) { in bnx2x_hc_int_disable()
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
871 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
872 if (REG_RD(bp, addr) != val) in bnx2x_hc_int_disable()
876 static void bnx2x_igu_int_disable(struct bnx2x *bp) in bnx2x_igu_int_disable() argument
878 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_disable()
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
890 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) in bnx2x_igu_int_disable()
894 static void bnx2x_int_disable(struct bnx2x *bp) in bnx2x_int_disable() argument
896 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_disable()
897 bnx2x_hc_int_disable(bp); in bnx2x_int_disable()
899 bnx2x_igu_int_disable(bp); in bnx2x_int_disable()
902 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) in bnx2x_panic_dump() argument
907 int func = BP_FUNC(bp); in bnx2x_panic_dump()
912 if (IS_PF(bp) && disable_int) in bnx2x_panic_dump()
913 bnx2x_int_disable(bp); in bnx2x_panic_dump()
915 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_panic_dump()
916 bp->eth_stats.unrecoverable_error++; in bnx2x_panic_dump()
923 if (IS_PF(bp)) { in bnx2x_panic_dump()
924 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_panic_dump()
928 bp->def_idx, bp->def_att_idx, bp->attn_state, in bnx2x_panic_dump()
929 bp->spq_prod_idx, bp->stats_counter); in bnx2x_panic_dump()
946 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + in bnx2x_panic_dump()
959 for_each_eth_queue(bp, i) { in bnx2x_panic_dump()
960 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
965 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
969 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
976 if (!bp->fp) in bnx2x_panic_dump()
1009 loop = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1030 if (IS_VF(bp)) in bnx2x_panic_dump()
1034 data_size = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1038 sb_data_p = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1043 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + in bnx2x_panic_dump()
1047 if (!CHIP_IS_E1x(bp)) { in bnx2x_panic_dump()
1084 if (IS_PF(bp)) { in bnx2x_panic_dump()
1086 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); in bnx2x_panic_dump()
1088 u32 *data = (u32 *)&bp->eq_ring[i].message.data; in bnx2x_panic_dump()
1091 i, bp->eq_ring[i].message.opcode, in bnx2x_panic_dump()
1092 bp->eq_ring[i].message.error); in bnx2x_panic_dump()
1100 for_each_valid_rx_queue(bp, i) { in bnx2x_panic_dump()
1101 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1103 if (!bp->fp) in bnx2x_panic_dump()
1140 for_each_valid_tx_queue(bp, i) { in bnx2x_panic_dump()
1141 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1143 if (!bp->fp) in bnx2x_panic_dump()
1178 if (IS_PF(bp)) { in bnx2x_panic_dump()
1179 bnx2x_fw_dump(bp); in bnx2x_panic_dump()
1180 bnx2x_mc_assert(bp); in bnx2x_panic_dump()
1208 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_buf_flushed() argument
1215 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1216 crd = crd_start = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1217 init_crd = REG_RD(bp, regs->init_crd); in bnx2x_pbf_pN_buf_flushed()
1227 crd = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1228 crd_freed = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1243 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_cmd_flushed() argument
1250 occup = to_free = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1251 freed = freed_start = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1259 occup = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1260 freed = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1275 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_reg_poll() argument
1281 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) in bnx2x_flr_clnup_reg_poll()
1287 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_poll_hw_counter() argument
1290 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); in bnx2x_flr_clnup_poll_hw_counter()
1299 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) in bnx2x_flr_clnup_poll_count() argument
1302 if (CHIP_REV_IS_EMUL(bp)) in bnx2x_flr_clnup_poll_count()
1305 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_flr_clnup_poll_count()
1311 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) in bnx2x_tx_hw_flushed() argument
1314 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1317 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1320 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1323 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1326 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1329 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1335 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1338 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1341 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1344 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1347 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1350 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1353 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1356 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1359 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1368 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1372 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1384 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) in bnx2x_send_final_clnup() argument
1391 if (REG_RD(bp, comp_addr)) { in bnx2x_send_final_clnup()
1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1404 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { in bnx2x_send_final_clnup()
1407 (REG_RD(bp, comp_addr))); in bnx2x_send_final_clnup()
1412 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1427 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) in bnx2x_poll_hw_usage_counters() argument
1430 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1437 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1445 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), in bnx2x_poll_hw_usage_counters()
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1452 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1456 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1457 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1463 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1464 dmae_reg_go_c[INIT_DMAE_C(bp)], in bnx2x_poll_hw_usage_counters()
1472 static void bnx2x_hw_enable_status(struct bnx2x *bp) in bnx2x_hw_enable_status() argument
1476 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); in bnx2x_hw_enable_status()
1479 val = REG_RD(bp, PBF_REG_DISABLE_PF); in bnx2x_hw_enable_status()
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); in bnx2x_hw_enable_status()
1485 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); in bnx2x_hw_enable_status()
1488 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); in bnx2x_hw_enable_status()
1491 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in bnx2x_hw_enable_status()
1494 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in bnx2x_hw_enable_status()
1497 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in bnx2x_hw_enable_status()
1502 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) in bnx2x_pf_flr_clnup() argument
1504 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); in bnx2x_pf_flr_clnup()
1506 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); in bnx2x_pf_flr_clnup()
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
1513 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) in bnx2x_pf_flr_clnup()
1519 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) in bnx2x_pf_flr_clnup()
1525 bnx2x_tx_hw_flushed(bp, poll_cnt); in bnx2x_pf_flr_clnup()
1531 if (bnx2x_is_pcie_pending(bp->pdev)) in bnx2x_pf_flr_clnup()
1535 bnx2x_hw_enable_status(bp); in bnx2x_pf_flr_clnup()
1541 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_pf_flr_clnup()
1546 static void bnx2x_hc_int_enable(struct bnx2x *bp) in bnx2x_hc_int_enable() argument
1548 int port = BP_PORT(bp); in bnx2x_hc_int_enable()
1550 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_enable()
1551 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1552 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1553 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_hc_int_enable()
1573 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1577 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1583 if (CHIP_IS_E1(bp)) in bnx2x_hc_int_enable()
1584 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1590 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1597 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1599 if (IS_MF(bp)) { in bnx2x_hc_int_enable()
1600 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_hc_int_enable()
1601 if (bp->port.pmf) in bnx2x_hc_int_enable()
1607 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1608 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1615 static void bnx2x_igu_int_enable(struct bnx2x *bp) in bnx2x_igu_int_enable() argument
1618 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1619 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1620 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_igu_int_enable()
1622 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_enable()
1646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1647 bnx2x_ack_int(bp); in bnx2x_igu_int_enable()
1655 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1658 pci_intx(bp->pdev, true); in bnx2x_igu_int_enable()
1663 if (IS_MF(bp)) { in bnx2x_igu_int_enable()
1664 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_igu_int_enable()
1665 if (bp->port.pmf) in bnx2x_igu_int_enable()
1671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1678 void bnx2x_int_enable(struct bnx2x *bp) in bnx2x_int_enable() argument
1680 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_enable()
1681 bnx2x_hc_int_enable(bp); in bnx2x_int_enable()
1683 bnx2x_igu_int_enable(bp); in bnx2x_int_enable()
1686 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) in bnx2x_int_disable_sync() argument
1688 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_int_disable_sync()
1693 bnx2x_int_disable(bp); in bnx2x_int_disable_sync()
1697 synchronize_irq(bp->msix_table[0].vector); in bnx2x_int_disable_sync()
1699 if (CNIC_SUPPORT(bp)) in bnx2x_int_disable_sync()
1701 for_each_eth_queue(bp, i) in bnx2x_int_disable_sync()
1702 synchronize_irq(bp->msix_table[offset++].vector); in bnx2x_int_disable_sync()
1704 synchronize_irq(bp->pdev->irq); in bnx2x_int_disable_sync()
1707 cancel_delayed_work(&bp->sp_task); in bnx2x_int_disable_sync()
1708 cancel_delayed_work(&bp->period_task); in bnx2x_int_disable_sync()
1719 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_trylock_hw_lock() argument
1723 int func = BP_FUNC(bp); in bnx2x_trylock_hw_lock()
1744 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
1745 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_trylock_hw_lock()
1762 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) in bnx2x_get_leader_lock_resource() argument
1764 if (BP_PATH(bp)) in bnx2x_get_leader_lock_resource()
1777 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) in bnx2x_trylock_leader_lock() argument
1779 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_trylock_leader_lock()
1782 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1785 static int bnx2x_schedule_sp_task(struct bnx2x *bp) in bnx2x_schedule_sp_task() argument
1791 atomic_set(&bp->interrupt_occurred, 1); in bnx2x_schedule_sp_task()
1800 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); in bnx2x_schedule_sp_task()
1805 struct bnx2x *bp = fp->bp; in bnx2x_sp_event() local
1809 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_sp_event()
1813 fp->index, cid, command, bp->state, in bnx2x_sp_event()
1821 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); in bnx2x_sp_event()
1866 q_obj->complete_cmd(bp, q_obj, drv_cmd)) in bnx2x_sp_event()
1881 atomic_inc(&bp->cq_spq_left); in bnx2x_sp_event()
1885 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); in bnx2x_sp_event()
1888 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { in bnx2x_sp_event()
1899 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); in bnx2x_sp_event()
1901 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_sp_event()
1905 bnx2x_schedule_sp_task(bp); in bnx2x_sp_event()
1913 struct bnx2x *bp = netdev_priv(dev_instance); in bnx2x_interrupt() local
1914 u16 status = bnx2x_ack_int(bp); in bnx2x_interrupt()
1927 if (unlikely(bp->panic)) in bnx2x_interrupt()
1931 for_each_eth_queue(bp, i) { in bnx2x_interrupt()
1932 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_interrupt()
1934 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); in bnx2x_interrupt()
1940 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); in bnx2x_interrupt()
1945 if (CNIC_SUPPORT(bp)) { in bnx2x_interrupt()
1951 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_interrupt()
1952 if (c_ops && (bp->cnic_eth_dev.drv_state & in bnx2x_interrupt()
1954 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_interrupt()
1966 bnx2x_schedule_sp_task(bp); in bnx2x_interrupt()
1986 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_acquire_hw_lock() argument
1990 int func = BP_FUNC(bp); in bnx2x_acquire_hw_lock()
2009 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2019 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
2020 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2030 int bnx2x_release_leader_lock(struct bnx2x *bp) in bnx2x_release_leader_lock() argument
2032 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_release_leader_lock()
2035 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_release_hw_lock() argument
2039 int func = BP_FUNC(bp); in bnx2x_release_hw_lock()
2057 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_release_hw_lock()
2064 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
2068 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) in bnx2x_get_gpio() argument
2071 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_get_gpio()
2072 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_get_gpio()
2085 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_get_gpio()
2096 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio() argument
2099 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio()
2100 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio()
2111 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2113 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in bnx2x_set_gpio()
2146 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
2147 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2152 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) in bnx2x_set_mult_gpio() argument
2159 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2161 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_set_mult_gpio()
2192 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_mult_gpio()
2194 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2199 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio_int() argument
2202 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio_int()
2203 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio_int()
2214 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2216 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); in bnx2x_set_gpio_int()
2241 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
2242 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2247 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) in bnx2x_set_spio() argument
2257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2259 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); in bnx2x_set_spio()
2286 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2287 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2292 void bnx2x_calc_fc_adv(struct bnx2x *bp) in bnx2x_calc_fc_adv() argument
2294 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_calc_fc_adv()
2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2298 switch (bp->link_vars.ieee_fc & in bnx2x_calc_fc_adv()
2301 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2306 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; in bnx2x_calc_fc_adv()
2314 static void bnx2x_set_requested_fc(struct bnx2x *bp) in bnx2x_set_requested_fc() argument
2320 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) in bnx2x_set_requested_fc()
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; in bnx2x_set_requested_fc()
2323 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; in bnx2x_set_requested_fc()
2326 static void bnx2x_init_dropless_fc(struct bnx2x *bp) in bnx2x_init_dropless_fc() argument
2330 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { in bnx2x_init_dropless_fc()
2331 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_init_dropless_fc()
2334 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_dropless_fc()
2335 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), in bnx2x_init_dropless_fc()
2343 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) in bnx2x_initial_phy_init() argument
2345 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_initial_phy_init()
2346 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; in bnx2x_initial_phy_init()
2348 if (!BP_NOMCP(bp)) { in bnx2x_initial_phy_init()
2349 bnx2x_set_requested_fc(bp); in bnx2x_initial_phy_init()
2350 bnx2x_acquire_phy_lock(bp); in bnx2x_initial_phy_init()
2353 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2372 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2376 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_initial_phy_init()
2378 bnx2x_release_phy_lock(bp); in bnx2x_initial_phy_init()
2380 bnx2x_init_dropless_fc(bp); in bnx2x_initial_phy_init()
2382 bnx2x_calc_fc_adv(bp); in bnx2x_initial_phy_init()
2384 if (bp->link_vars.link_up) { in bnx2x_initial_phy_init()
2385 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_initial_phy_init()
2386 bnx2x_link_report(bp); in bnx2x_initial_phy_init()
2388 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_initial_phy_init()
2389 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; in bnx2x_initial_phy_init()
2396 void bnx2x_link_set(struct bnx2x *bp) in bnx2x_link_set() argument
2398 if (!BP_NOMCP(bp)) { in bnx2x_link_set()
2399 bnx2x_acquire_phy_lock(bp); in bnx2x_link_set()
2400 bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_link_set()
2401 bnx2x_release_phy_lock(bp); in bnx2x_link_set()
2403 bnx2x_init_dropless_fc(bp); in bnx2x_link_set()
2405 bnx2x_calc_fc_adv(bp); in bnx2x_link_set()
2410 static void bnx2x__link_reset(struct bnx2x *bp) in bnx2x__link_reset() argument
2412 if (!BP_NOMCP(bp)) { in bnx2x__link_reset()
2413 bnx2x_acquire_phy_lock(bp); in bnx2x__link_reset()
2414 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); in bnx2x__link_reset()
2415 bnx2x_release_phy_lock(bp); in bnx2x__link_reset()
2420 void bnx2x_force_link_reset(struct bnx2x *bp) in bnx2x_force_link_reset() argument
2422 bnx2x_acquire_phy_lock(bp); in bnx2x_force_link_reset()
2423 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); in bnx2x_force_link_reset()
2424 bnx2x_release_phy_lock(bp); in bnx2x_force_link_reset()
2427 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) in bnx2x_link_test() argument
2431 if (!BP_NOMCP(bp)) { in bnx2x_link_test()
2432 bnx2x_acquire_phy_lock(bp); in bnx2x_link_test()
2433 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, in bnx2x_link_test()
2435 bnx2x_release_phy_lock(bp); in bnx2x_link_test()
2451 static void bnx2x_calc_vn_min(struct bnx2x *bp, in bnx2x_calc_vn_min() argument
2457 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_calc_vn_min()
2458 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_min()
2475 if (BNX2X_IS_ETS_ENABLED(bp)) { in bnx2x_calc_vn_min()
2489 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, in bnx2x_calc_vn_max() argument
2493 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_max()
2498 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); in bnx2x_calc_vn_max()
2500 if (IS_MF_PERCENT_BW(bp)) { in bnx2x_calc_vn_max()
2502 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; in bnx2x_calc_vn_max()
2513 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) in bnx2x_get_cmng_fns_mode() argument
2515 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_get_cmng_fns_mode()
2517 if (IS_MF(bp)) in bnx2x_get_cmng_fns_mode()
2523 void bnx2x_read_mf_cfg(struct bnx2x *bp) in bnx2x_read_mf_cfg() argument
2525 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); in bnx2x_read_mf_cfg()
2527 if (BP_NOMCP(bp)) in bnx2x_read_mf_cfg()
2541 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_read_mf_cfg()
2542 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); in bnx2x_read_mf_cfg()
2547 bp->mf_config[vn] = in bnx2x_read_mf_cfg()
2548 MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_read_mf_cfg()
2550 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_read_mf_cfg()
2552 bp->flags |= MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2555 bp->flags &= ~MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2559 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) in bnx2x_cmng_fns_init() argument
2564 input.port_rate = bp->link_vars.line_speed; in bnx2x_cmng_fns_init()
2571 bnx2x_read_mf_cfg(bp); in bnx2x_cmng_fns_init()
2574 bnx2x_calc_vn_min(bp, &input); in bnx2x_cmng_fns_init()
2577 if (bp->port.pmf) in bnx2x_cmng_fns_init()
2578 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) in bnx2x_cmng_fns_init()
2579 bnx2x_calc_vn_max(bp, vn, &input); in bnx2x_cmng_fns_init()
2585 bnx2x_init_cmng(&input, &bp->cmng); in bnx2x_cmng_fns_init()
2594 static void storm_memset_cmng(struct bnx2x *bp, in storm_memset_cmng() argument
2604 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); in storm_memset_cmng()
2606 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in storm_memset_cmng()
2607 int func = func_by_vn(bp, vn); in storm_memset_cmng()
2612 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2618 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2624 void bnx2x_set_local_cmng(struct bnx2x *bp) in bnx2x_set_local_cmng() argument
2626 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); in bnx2x_set_local_cmng()
2629 bnx2x_cmng_fns_init(bp, false, cmng_fns); in bnx2x_set_local_cmng()
2630 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_set_local_cmng()
2639 static void bnx2x_link_attn(struct bnx2x *bp) in bnx2x_link_attn() argument
2642 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x_link_attn()
2644 bnx2x_link_update(&bp->link_params, &bp->link_vars); in bnx2x_link_attn()
2646 bnx2x_init_dropless_fc(bp); in bnx2x_link_attn()
2648 if (bp->link_vars.link_up) { in bnx2x_link_attn()
2650 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { in bnx2x_link_attn()
2653 pstats = bnx2x_sp(bp, port_stats); in bnx2x_link_attn()
2658 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_link_attn()
2659 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_link_attn()
2662 if (bp->link_vars.link_up && bp->link_vars.line_speed) in bnx2x_link_attn()
2663 bnx2x_set_local_cmng(bp); in bnx2x_link_attn()
2665 __bnx2x_link_report(bp); in bnx2x_link_attn()
2667 if (IS_MF(bp)) in bnx2x_link_attn()
2668 bnx2x_link_sync_notify(bp); in bnx2x_link_attn()
2671 void bnx2x__link_status_update(struct bnx2x *bp) in bnx2x__link_status_update() argument
2673 if (bp->state != BNX2X_STATE_OPEN) in bnx2x__link_status_update()
2677 if (IS_PF(bp)) { in bnx2x__link_status_update()
2678 bnx2x_dcbx_pmf_update(bp); in bnx2x__link_status_update()
2679 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); in bnx2x__link_status_update()
2680 if (bp->link_vars.link_up) in bnx2x__link_status_update()
2681 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2683 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x__link_status_update()
2685 bnx2x_link_report(bp); in bnx2x__link_status_update()
2688 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | in bnx2x__link_status_update()
2700 bp->port.advertising[0] = bp->port.supported[0]; in bnx2x__link_status_update()
2702 bp->link_params.bp = bp; in bnx2x__link_status_update()
2703 bp->link_params.port = BP_PORT(bp); in bnx2x__link_status_update()
2704 bp->link_params.req_duplex[0] = DUPLEX_FULL; in bnx2x__link_status_update()
2705 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2706 bp->link_params.req_line_speed[0] = SPEED_10000; in bnx2x__link_status_update()
2707 bp->link_params.speed_cap_mask[0] = 0x7f0000; in bnx2x__link_status_update()
2708 bp->link_params.switch_cfg = SWITCH_CFG_10G; in bnx2x__link_status_update()
2709 bp->link_vars.mac_type = MAC_TYPE_BMAC; in bnx2x__link_status_update()
2710 bp->link_vars.line_speed = SPEED_10000; in bnx2x__link_status_update()
2711 bp->link_vars.link_status = in bnx2x__link_status_update()
2714 bp->link_vars.link_up = 1; in bnx2x__link_status_update()
2715 bp->link_vars.duplex = DUPLEX_FULL; in bnx2x__link_status_update()
2716 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2717 __bnx2x_link_report(bp); in bnx2x__link_status_update()
2719 bnx2x_sample_bulletin(bp); in bnx2x__link_status_update()
2726 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2730 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, in bnx2x_afex_func_update() argument
2737 func_params.f_obj = &bp->func_obj; in bnx2x_afex_func_update()
2749 if (bnx2x_func_state_change(bp, &func_params) < 0) in bnx2x_afex_func_update()
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_afex_func_update()
2755 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, in bnx2x_afex_handle_vif_list_cmd() argument
2769 func_params.f_obj = &bp->func_obj; in bnx2x_afex_handle_vif_list_cmd()
2786 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_afex_handle_vif_list_cmd()
2788 bnx2x_fw_command(bp, drv_msg_code, 0); in bnx2x_afex_handle_vif_list_cmd()
2793 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) in bnx2x_handle_afex_cmd() argument
2796 u32 func = BP_ABS_FUNC(bp); in bnx2x_handle_afex_cmd()
2806 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2809 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); in bnx2x_handle_afex_cmd()
2813 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2814 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2818 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, in bnx2x_handle_afex_cmd()
2823 addr_to_write = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2824 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2825 stats_type = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2826 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2832 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); in bnx2x_handle_afex_cmd()
2836 REG_WR(bp, addr_to_write + i*sizeof(u32), in bnx2x_handle_afex_cmd()
2840 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); in bnx2x_handle_afex_cmd()
2844 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_handle_afex_cmd()
2845 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2857 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); in bnx2x_handle_afex_cmd()
2859 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2861 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); in bnx2x_handle_afex_cmd()
2863 cmng_input.vnic_max_rate[BP_VN(bp)]; in bnx2x_handle_afex_cmd()
2868 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); in bnx2x_handle_afex_cmd()
2872 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2884 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2889 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2895 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, in bnx2x_handle_afex_cmd()
2899 bp->afex_def_vlan_tag = vlan_val; in bnx2x_handle_afex_cmd()
2900 bp->afex_vlan_mode = vlan_mode; in bnx2x_handle_afex_cmd()
2903 bnx2x_link_report(bp); in bnx2x_handle_afex_cmd()
2906 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); in bnx2x_handle_afex_cmd()
2909 bp->afex_def_vlan_tag = -1; in bnx2x_handle_afex_cmd()
2914 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) in bnx2x_handle_update_svid_cmd() argument
2921 func_params.f_obj = &bp->func_obj; in bnx2x_handle_update_svid_cmd()
2924 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { in bnx2x_handle_update_svid_cmd()
2925 int func = BP_ABS_FUNC(bp); in bnx2x_handle_update_svid_cmd()
2929 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_update_svid_cmd()
2932 bp->mf_ov = val; in bnx2x_handle_update_svid_cmd()
2939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, in bnx2x_handle_update_svid_cmd()
2940 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2945 switch_update_params->vlan = bp->mf_ov; in bnx2x_handle_update_svid_cmd()
2947 if (bnx2x_func_state_change(bp, &func_params) < 0) { in bnx2x_handle_update_svid_cmd()
2949 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2953 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2959 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); in bnx2x_handle_update_svid_cmd()
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); in bnx2x_handle_update_svid_cmd()
2965 static void bnx2x_pmf_update(struct bnx2x *bp) in bnx2x_pmf_update() argument
2967 int port = BP_PORT(bp); in bnx2x_pmf_update()
2970 bp->port.pmf = 1; in bnx2x_pmf_update()
2971 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); in bnx2x_pmf_update()
2980 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_pmf_update()
2982 bnx2x_dcbx_pmf_update(bp); in bnx2x_pmf_update()
2985 val = (0xff0f | (1 << (BP_VN(bp) + 4))); in bnx2x_pmf_update()
2986 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_pmf_update()
2987 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2988 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2989 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_pmf_update()
2990 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
2991 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
2994 bnx2x_stats_handle(bp, STATS_EVENT_PMF); in bnx2x_pmf_update()
3006 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) in bnx2x_fw_command() argument
3008 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_fw_command()
3012 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; in bnx2x_fw_command()
3014 mutex_lock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3015 seq = ++bp->fw_seq; in bnx2x_fw_command()
3016 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); in bnx2x_fw_command()
3017 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); in bnx2x_fw_command()
3026 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); in bnx2x_fw_command()
3040 bnx2x_fw_dump(bp); in bnx2x_fw_command()
3043 mutex_unlock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3048 static void storm_memset_func_cfg(struct bnx2x *bp, in storm_memset_func_cfg() argument
3057 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); in storm_memset_func_cfg()
3060 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) in bnx2x_func_init() argument
3062 if (CHIP_IS_E1x(bp)) { in bnx2x_func_init()
3065 storm_memset_func_cfg(bp, &tcfg, p->func_id); in bnx2x_func_init()
3069 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); in bnx2x_func_init()
3070 storm_memset_func_en(bp, p->func_id, 1); in bnx2x_func_init()
3074 storm_memset_spq_addr(bp, p->spq_map, p->func_id); in bnx2x_func_init()
3075 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
3089 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, in bnx2x_get_common_flags() argument
3107 if (bp->flags & TX_SWITCHING) in bnx2x_get_common_flags()
3120 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, in bnx2x_get_q_flags() argument
3127 if (IS_MF_SD(bp)) in bnx2x_get_q_flags()
3152 if (IS_MF_AFEX(bp)) in bnx2x_get_q_flags()
3155 return flags | bnx2x_get_common_flags(bp, fp, true); in bnx2x_get_q_flags()
3158 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, in bnx2x_pf_q_prep_general() argument
3169 gen_init->mtu = bp->dev->mtu; in bnx2x_pf_q_prep_general()
3176 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, in bnx2x_pf_rx_q_prep() argument
3185 pause->sge_th_lo = SGE_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3186 pause->sge_th_hi = SGE_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3189 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3194 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> in bnx2x_pf_rx_q_prep()
3202 if (!CHIP_IS_E1(bp)) { in bnx2x_pf_rx_q_prep()
3203 pause->bd_th_lo = BD_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3204 pause->bd_th_hi = BD_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3206 pause->rcq_th_lo = RCQ_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3207 pause->rcq_th_hi = RCQ_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3212 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3214 bp->rx_ring_size); in bnx2x_pf_rx_q_prep()
3215 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3238 rxq_init->rss_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3239 rxq_init->mcast_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3246 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); in bnx2x_pf_rx_q_prep()
3258 if (IS_MF_AFEX(bp)) { in bnx2x_pf_rx_q_prep()
3259 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; in bnx2x_pf_rx_q_prep()
3264 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, in bnx2x_pf_tx_q_prep() argument
3277 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); in bnx2x_pf_tx_q_prep()
3285 static void bnx2x_pf_init(struct bnx2x *bp) in bnx2x_pf_init() argument
3290 if (!CHIP_IS_E1x(bp)) { in bnx2x_pf_init()
3293 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3295 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3296 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3298 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3301 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3302 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3306 func_init.pf_id = BP_FUNC(bp); in bnx2x_pf_init()
3307 func_init.func_id = BP_FUNC(bp); in bnx2x_pf_init()
3308 func_init.spq_map = bp->spq_mapping; in bnx2x_pf_init()
3309 func_init.spq_prod = bp->spq_prod_idx; in bnx2x_pf_init()
3311 bnx2x_func_init(bp, &func_init); in bnx2x_pf_init()
3313 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); in bnx2x_pf_init()
3321 bp->link_vars.line_speed = SPEED_10000; in bnx2x_pf_init()
3322 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); in bnx2x_pf_init()
3325 if (bp->port.pmf) in bnx2x_pf_init()
3326 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_pf_init()
3329 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); in bnx2x_pf_init()
3330 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); in bnx2x_pf_init()
3331 eq_data.producer = bp->eq_prod; in bnx2x_pf_init()
3334 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); in bnx2x_pf_init()
3337 static void bnx2x_e1h_disable(struct bnx2x *bp) in bnx2x_e1h_disable() argument
3339 int port = BP_PORT(bp); in bnx2x_e1h_disable()
3341 bnx2x_tx_disable(bp); in bnx2x_e1h_disable()
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3346 static void bnx2x_e1h_enable(struct bnx2x *bp) in bnx2x_e1h_enable() argument
3348 int port = BP_PORT(bp); in bnx2x_e1h_enable()
3350 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) in bnx2x_e1h_enable()
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_e1h_enable()
3354 netif_tx_wake_all_queues(bp->dev); in bnx2x_e1h_enable()
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) in bnx2x_drv_info_ether_stat() argument
3367 &bp->slowpath->drv_info_to_mcp.ether_stat; in bnx2x_drv_info_ether_stat()
3369 &bp->sp_objs->mac_obj; in bnx2x_drv_info_ether_stat()
3386 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, in bnx2x_drv_info_ether_stat()
3390 ether_stat->mtu_size = bp->dev->mtu; in bnx2x_drv_info_ether_stat()
3391 if (bp->dev->features & NETIF_F_RXCSUM) in bnx2x_drv_info_ether_stat()
3393 if (bp->dev->features & NETIF_F_TSO) in bnx2x_drv_info_ether_stat()
3395 ether_stat->feature_flags |= bp->common.boot_mode; in bnx2x_drv_info_ether_stat()
3397 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; in bnx2x_drv_info_ether_stat()
3399 ether_stat->txq_size = bp->tx_ring_size; in bnx2x_drv_info_ether_stat()
3400 ether_stat->rxq_size = bp->rx_ring_size; in bnx2x_drv_info_ether_stat()
3403 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; in bnx2x_drv_info_ether_stat()
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) in bnx2x_drv_info_fcoe_stat() argument
3409 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_fcoe_stat()
3411 &bp->slowpath->drv_info_to_mcp.fcoe_stat; in bnx2x_drv_info_fcoe_stat()
3413 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_fcoe_stat()
3416 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); in bnx2x_drv_info_fcoe_stat()
3422 if (!NO_FCOE(bp)) { in bnx2x_drv_info_fcoe_stat()
3424 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3432 &bp->fw_stats_data->fcoe; in bnx2x_drv_info_fcoe_stat()
3506 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); in bnx2x_drv_info_fcoe_stat()
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) in bnx2x_drv_info_iscsi_stat() argument
3511 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_iscsi_stat()
3513 &bp->slowpath->drv_info_to_mcp.iscsi_stat; in bnx2x_drv_info_iscsi_stat()
3515 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_iscsi_stat()
3518 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, in bnx2x_drv_info_iscsi_stat()
3525 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); in bnx2x_drv_info_iscsi_stat()
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp) in bnx2x_config_mf_bw() argument
3535 if (bp->link_vars.link_up) { in bnx2x_config_mf_bw()
3536 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); in bnx2x_config_mf_bw()
3537 bnx2x_link_sync_notify(bp); in bnx2x_config_mf_bw()
3539 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_config_mf_bw()
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp) in bnx2x_set_mf_bw() argument
3544 bnx2x_config_mf_bw(bp); in bnx2x_set_mf_bw()
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); in bnx2x_set_mf_bw()
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp) in bnx2x_handle_eee_event() argument
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); in bnx2x_handle_eee_event()
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) in bnx2x_handle_drv_info_req() argument
3560 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); in bnx2x_handle_drv_info_req()
3566 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3574 mutex_lock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3576 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_handle_drv_info_req()
3581 bnx2x_drv_info_ether_stat(bp); in bnx2x_handle_drv_info_req()
3584 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_handle_drv_info_req()
3587 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_handle_drv_info_req()
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3598 SHMEM2_WR(bp, drv_info_host_addr_lo, in bnx2x_handle_drv_info_req()
3599 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3600 SHMEM2_WR(bp, drv_info_host_addr_hi, in bnx2x_handle_drv_info_req()
3601 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); in bnx2x_handle_drv_info_req()
3609 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { in bnx2x_handle_drv_info_req()
3611 } else if (!bp->drv_info_mng_owner) { in bnx2x_handle_drv_info_req()
3612 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); in bnx2x_handle_drv_info_req()
3615 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); in bnx2x_handle_drv_info_req()
3619 SHMEM2_WR(bp, mfw_drv_indication, in bnx2x_handle_drv_info_req()
3630 bp->drv_info_mng_owner = true; in bnx2x_handle_drv_info_req()
3634 mutex_unlock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3658 void bnx2x_update_mng_version(struct bnx2x *bp) in bnx2x_update_mng_version() argument
3663 int idx = BP_FW_MB_IDX(bp); in bnx2x_update_mng_version()
3666 if (!SHMEM2_HAS(bp, func_os_drv_ver)) in bnx2x_update_mng_version()
3669 mutex_lock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3671 if (bp->drv_info_mng_owner) in bnx2x_update_mng_version()
3674 if (bp->state != BNX2X_STATE_OPEN) in bnx2x_update_mng_version()
3679 if (!CNIC_LOADED(bp)) in bnx2x_update_mng_version()
3683 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3685 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_update_mng_version()
3686 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; in bnx2x_update_mng_version()
3689 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3691 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_update_mng_version()
3692 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; in bnx2x_update_mng_version()
3696 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); in bnx2x_update_mng_version()
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); in bnx2x_update_mng_version()
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); in bnx2x_update_mng_version()
3700 mutex_unlock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3706 void bnx2x_update_mfw_dump(struct bnx2x *bp) in bnx2x_update_mfw_dump() argument
3711 if (!SHMEM2_HAS(bp, drv_info)) in bnx2x_update_mfw_dump()
3715 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); in bnx2x_update_mfw_dump()
3718 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); in bnx2x_update_mfw_dump()
3720 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); in bnx2x_update_mfw_dump()
3723 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); in bnx2x_update_mfw_dump()
3732 static void bnx2x_oem_event(struct bnx2x *bp, u32 event) in bnx2x_oem_event() argument
3759 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_oem_event()
3761 bp->flags |= MF_FUNC_DIS; in bnx2x_oem_event()
3763 bnx2x_e1h_disable(bp); in bnx2x_oem_event()
3766 bp->flags &= ~MF_FUNC_DIS; in bnx2x_oem_event()
3768 bnx2x_e1h_enable(bp); in bnx2x_oem_event()
3776 bnx2x_config_mf_bw(bp); in bnx2x_oem_event()
3783 bnx2x_fw_command(bp, cmd_fail, 0); in bnx2x_oem_event()
3785 bnx2x_fw_command(bp, cmd_ok, 0); in bnx2x_oem_event()
3789 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) in bnx2x_sp_get_next() argument
3791 struct eth_spe *next_spe = bp->spq_prod_bd; in bnx2x_sp_get_next()
3793 if (bp->spq_prod_bd == bp->spq_last_bd) { in bnx2x_sp_get_next()
3794 bp->spq_prod_bd = bp->spq; in bnx2x_sp_get_next()
3795 bp->spq_prod_idx = 0; in bnx2x_sp_get_next()
3798 bp->spq_prod_bd++; in bnx2x_sp_get_next()
3799 bp->spq_prod_idx++; in bnx2x_sp_get_next()
3805 static void bnx2x_sp_prod_update(struct bnx2x *bp) in bnx2x_sp_prod_update() argument
3807 int func = BP_FUNC(bp); in bnx2x_sp_prod_update()
3816 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), in bnx2x_sp_prod_update()
3817 bp->spq_prod_idx); in bnx2x_sp_prod_update()
3855 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, in bnx2x_sp_post() argument
3863 if (unlikely(bp->panic)) { in bnx2x_sp_post()
3869 spin_lock_bh(&bp->spq_lock); in bnx2x_sp_post()
3872 if (!atomic_read(&bp->eq_spq_left)) { in bnx2x_sp_post()
3874 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3878 } else if (!atomic_read(&bp->cq_spq_left)) { in bnx2x_sp_post()
3880 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3885 spe = bnx2x_sp_get_next(bp); in bnx2x_sp_post()
3890 HW_CID(bp, cid)); in bnx2x_sp_post()
3899 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & in bnx2x_sp_post()
3916 atomic_dec(&bp->eq_spq_left); in bnx2x_sp_post()
3918 atomic_dec(&bp->cq_spq_left); in bnx2x_sp_post()
3922 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), in bnx2x_sp_post()
3923 (u32)(U64_LO(bp->spq_mapping) + in bnx2x_sp_post()
3924 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, in bnx2x_sp_post()
3925 HW_CID(bp, cid), data_hi, data_lo, type, in bnx2x_sp_post()
3926 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); in bnx2x_sp_post()
3928 bnx2x_sp_prod_update(bp); in bnx2x_sp_post()
3929 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3934 static int bnx2x_acquire_alr(struct bnx2x *bp) in bnx2x_acquire_alr() argument
3941 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); in bnx2x_acquire_alr()
3942 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); in bnx2x_acquire_alr()
3957 static void bnx2x_release_alr(struct bnx2x *bp) in bnx2x_release_alr() argument
3959 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
3965 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) in bnx2x_update_dsb_idx() argument
3967 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_update_dsb_idx()
3971 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { in bnx2x_update_dsb_idx()
3972 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; in bnx2x_update_dsb_idx()
3976 if (bp->def_idx != def_sb->sp_sb.running_index) { in bnx2x_update_dsb_idx()
3977 bp->def_idx = def_sb->sp_sb.running_index; in bnx2x_update_dsb_idx()
3990 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) in bnx2x_attn_int_asserted() argument
3992 int port = BP_PORT(bp); in bnx2x_attn_int_asserted()
4001 if (bp->attn_state & asserted) in bnx2x_attn_int_asserted()
4004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
4005 aeu_mask = REG_RD(bp, aeu_addr); in bnx2x_attn_int_asserted()
4012 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
4013 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
4015 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4016 bp->attn_state |= asserted; in bnx2x_attn_int_asserted()
4017 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4022 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_asserted()
4025 nig_mask = REG_RD(bp, nig_int_mask_addr); in bnx2x_attn_int_asserted()
4031 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4033 bnx2x_link_attn(bp); in bnx2x_attn_int_asserted()
4053 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4057 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4061 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4066 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4074 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4080 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_asserted()
4087 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_asserted()
4088 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
4095 if (bp->common.int_block != INT_BLOCK_HC) { in bnx2x_attn_int_asserted()
4098 igu_acked = REG_RD(bp, in bnx2x_attn_int_asserted()
4107 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
4108 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_asserted()
4112 static void bnx2x_fan_failure(struct bnx2x *bp) in bnx2x_fan_failure() argument
4114 int port = BP_PORT(bp); in bnx2x_fan_failure()
4118 SHMEM_RD(bp, in bnx2x_fan_failure()
4123 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, in bnx2x_fan_failure()
4127 …netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card … in bnx2x_fan_failure()
4134 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); in bnx2x_fan_failure()
4137 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted0() argument
4139 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted0()
4148 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4150 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4155 bnx2x_hw_reset_phy(&bp->link_params); in bnx2x_attn_int_deasserted0()
4156 bnx2x_fan_failure(bp); in bnx2x_attn_int_deasserted0()
4159 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { in bnx2x_attn_int_deasserted0()
4160 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4161 bnx2x_handle_module_detect_int(&bp->link_params); in bnx2x_attn_int_deasserted0()
4162 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4167 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4169 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4177 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted1() argument
4183 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); in bnx2x_attn_int_deasserted1()
4192 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted1()
4198 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted1()
4200 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
4208 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted2() argument
4214 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); in bnx2x_attn_int_deasserted2()
4222 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); in bnx2x_attn_int_deasserted2()
4228 if (!CHIP_IS_E1x(bp)) { in bnx2x_attn_int_deasserted2()
4229 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); in bnx2x_attn_int_deasserted2()
4236 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted2()
4242 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted2()
4244 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
4252 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted3() argument
4259 int func = BP_FUNC(bp); in bnx2x_attn_int_deasserted3()
4261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4262 bnx2x_read_mf_cfg(bp); in bnx2x_attn_int_deasserted3()
4263 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, in bnx2x_attn_int_deasserted3()
4264 func_mf_config[BP_ABS_FUNC(bp)].config); in bnx2x_attn_int_deasserted3()
4265 val = SHMEM_RD(bp, in bnx2x_attn_int_deasserted3()
4266 func_mb[BP_FW_MB_IDX(bp)].drv_status); in bnx2x_attn_int_deasserted3()
4270 bnx2x_oem_event(bp, in bnx2x_attn_int_deasserted3()
4275 bnx2x_set_mf_bw(bp); in bnx2x_attn_int_deasserted3()
4278 bnx2x_handle_drv_info_req(bp); in bnx2x_attn_int_deasserted3()
4281 bnx2x_schedule_iov_task(bp, in bnx2x_attn_int_deasserted3()
4284 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bnx2x_attn_int_deasserted3()
4285 bnx2x_pmf_update(bp); in bnx2x_attn_int_deasserted3()
4287 if (bp->port.pmf && in bnx2x_attn_int_deasserted3()
4289 bp->dcbx_enabled > 0) in bnx2x_attn_int_deasserted3()
4291 bnx2x_dcbx_set_params(bp, in bnx2x_attn_int_deasserted3()
4294 bnx2x_handle_afex_cmd(bp, in bnx2x_attn_int_deasserted3()
4297 bnx2x_handle_eee_event(bp); in bnx2x_attn_int_deasserted3()
4300 bnx2x_handle_update_svid_cmd(bp); in bnx2x_attn_int_deasserted3()
4302 if (bp->link_vars.periodic_flags & in bnx2x_attn_int_deasserted3()
4305 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4306 bp->link_vars.periodic_flags &= in bnx2x_attn_int_deasserted3()
4308 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4309 if (IS_MF(bp)) in bnx2x_attn_int_deasserted3()
4310 bnx2x_link_sync_notify(bp); in bnx2x_attn_int_deasserted3()
4311 bnx2x_link_report(bp); in bnx2x_attn_int_deasserted3()
4316 bnx2x__link_status_update(bp); in bnx2x_attn_int_deasserted3()
4320 bnx2x_mc_assert(bp); in bnx2x_attn_int_deasserted3()
4321 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4322 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4330 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4331 bnx2x_fw_dump(bp); in bnx2x_attn_int_deasserted3()
4340 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4341 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); in bnx2x_attn_int_deasserted3()
4345 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4346 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); in bnx2x_attn_int_deasserted3()
4349 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4382 void bnx2x_set_reset_global(struct bnx2x *bp) in bnx2x_set_reset_global() argument
4385 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4386 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_global()
4387 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); in bnx2x_set_reset_global()
4388 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4396 static void bnx2x_clear_reset_global(struct bnx2x *bp) in bnx2x_clear_reset_global() argument
4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_reset_global()
4401 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); in bnx2x_clear_reset_global()
4402 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4410 static bool bnx2x_reset_is_global(struct bnx2x *bp) in bnx2x_reset_is_global() argument
4412 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_global()
4423 static void bnx2x_set_reset_done(struct bnx2x *bp) in bnx2x_set_reset_done() argument
4426 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_done()
4428 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4429 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_done()
4433 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_done()
4435 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4443 void bnx2x_set_reset_in_progress(struct bnx2x *bp) in bnx2x_set_reset_in_progress() argument
4446 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_in_progress()
4448 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4449 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_in_progress()
4453 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_in_progress()
4454 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4461 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) in bnx2x_reset_is_done() argument
4463 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_done()
4476 void bnx2x_set_pf_load(struct bnx2x *bp) in bnx2x_set_pf_load() argument
4479 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_set_pf_load()
4481 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_set_pf_load()
4484 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4485 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_pf_load()
4493 val1 |= (1 << bp->pf_num); in bnx2x_set_pf_load()
4501 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_pf_load()
4502 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4514 bool bnx2x_clear_pf_load(struct bnx2x *bp) in bnx2x_clear_pf_load() argument
4517 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_clear_pf_load()
4519 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_clear_pf_load()
4522 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4523 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_pf_load()
4530 val1 &= ~(1 << bp->pf_num); in bnx2x_clear_pf_load()
4538 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_clear_pf_load()
4539 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4548 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) in bnx2x_get_load_status() argument
4554 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_get_load_status()
4566 static void _print_parity(struct bnx2x *bp, u32 reg) in _print_parity() argument
4568 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); in _print_parity()
4576 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity0() argument
4594 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4600 _print_parity(bp, PRS_REG_PRS_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4604 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4610 _print_parity(bp, SRC_REG_SRC_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4614 _print_parity(bp, TCM_REG_TCM_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4619 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4621 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4626 _print_parity(bp, GRCBASE_XPB + in bnx2x_check_blocks_with_parity0()
4640 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity1() argument
4658 _print_parity(bp, PBF_REG_PBF_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4664 _print_parity(bp, QM_REG_QM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4670 _print_parity(bp, TM_REG_TM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4676 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4683 _print_parity(bp, XCM_REG_XCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4690 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4692 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4700 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4707 if (CHIP_IS_E1x(bp)) { in bnx2x_check_blocks_with_parity1()
4708 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4711 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4713 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4728 _print_parity(bp, DBG_REG_DBG_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4734 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4741 _print_parity(bp, UCM_REG_UCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4748 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4750 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4757 _print_parity(bp, GRCBASE_UPB + in bnx2x_check_blocks_with_parity1()
4764 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4771 _print_parity(bp, CCM_REG_CCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4784 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity2() argument
4802 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4804 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4809 _print_parity(bp, PXP_REG_PXP_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4810 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4812 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4821 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4826 _print_parity(bp, CDU_REG_CDU_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4830 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4835 if (CHIP_IS_E1x(bp)) in bnx2x_check_blocks_with_parity2()
4836 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4839 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4844 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4858 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity3() argument
4894 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, in bnx2x_check_blocks_with_parity3()
4907 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity4() argument
4925 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4930 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4943 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, in bnx2x_parity_attn() argument
4968 netdev_err(bp->dev, in bnx2x_parity_attn()
4974 res |= bnx2x_check_blocks_with_parity0(bp, in bnx2x_parity_attn()
4976 res |= bnx2x_check_blocks_with_parity1(bp, in bnx2x_parity_attn()
4978 res |= bnx2x_check_blocks_with_parity2(bp, in bnx2x_parity_attn()
4980 res |= bnx2x_check_blocks_with_parity3(bp, in bnx2x_parity_attn()
4982 res |= bnx2x_check_blocks_with_parity4(bp, in bnx2x_parity_attn()
4999 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) in bnx2x_chk_parity_attn() argument
5002 int port = BP_PORT(bp); in bnx2x_chk_parity_attn()
5004 attn.sig[0] = REG_RD(bp, in bnx2x_chk_parity_attn()
5007 attn.sig[1] = REG_RD(bp, in bnx2x_chk_parity_attn()
5010 attn.sig[2] = REG_RD(bp, in bnx2x_chk_parity_attn()
5013 attn.sig[3] = REG_RD(bp, in bnx2x_chk_parity_attn()
5019 attn.sig[3] &= ((REG_RD(bp, in bnx2x_chk_parity_attn()
5025 if (!CHIP_IS_E1x(bp)) in bnx2x_chk_parity_attn()
5026 attn.sig[4] = REG_RD(bp, in bnx2x_chk_parity_attn()
5030 return bnx2x_parity_attn(bp, global, print, attn.sig); in bnx2x_chk_parity_attn()
5033 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted4() argument
5038 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5062 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5086 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) in bnx2x_attn_int_deasserted() argument
5089 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted()
5098 bnx2x_acquire_alr(bp); in bnx2x_attn_int_deasserted()
5100 if (bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_attn_int_deasserted()
5102 bp->recovery_state = BNX2X_RECOVERY_INIT; in bnx2x_attn_int_deasserted()
5103 schedule_delayed_work(&bp->sp_rtnl_task, 0); in bnx2x_attn_int_deasserted()
5105 bnx2x_int_disable(bp); in bnx2x_attn_int_deasserted()
5112 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5116 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5117 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5118 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5119 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5120 if (!CHIP_IS_E1x(bp)) in bnx2x_attn_int_deasserted()
5122 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5131 group_mask = &bp->attn_group[index]; in bnx2x_attn_int_deasserted()
5139 bnx2x_attn_int_deasserted4(bp, in bnx2x_attn_int_deasserted()
5141 bnx2x_attn_int_deasserted3(bp, in bnx2x_attn_int_deasserted()
5143 bnx2x_attn_int_deasserted1(bp, in bnx2x_attn_int_deasserted()
5145 bnx2x_attn_int_deasserted2(bp, in bnx2x_attn_int_deasserted()
5147 bnx2x_attn_int_deasserted0(bp, in bnx2x_attn_int_deasserted()
5152 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5154 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_deasserted()
5162 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_deasserted()
5163 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5165 if (~bp->attn_state & deasserted) in bnx2x_attn_int_deasserted()
5171 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5172 aeu_mask = REG_RD(bp, reg_addr); in bnx2x_attn_int_deasserted()
5179 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
5180 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5182 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5183 bp->attn_state &= ~deasserted; in bnx2x_attn_int_deasserted()
5184 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5187 static void bnx2x_attn_int(struct bnx2x *bp) in bnx2x_attn_int() argument
5190 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5192 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5194 u32 attn_state = bp->attn_state; in bnx2x_attn_int()
5209 bnx2x_attn_int_asserted(bp, asserted); in bnx2x_attn_int()
5212 bnx2x_attn_int_deasserted(bp, deasserted); in bnx2x_attn_int()
5215 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, in bnx2x_igu_ack_sb() argument
5218 u32 igu_addr = bp->igu_base_addr; in bnx2x_igu_ack_sb()
5220 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, in bnx2x_igu_ack_sb()
5224 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) in bnx2x_update_eq_prod() argument
5227 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); in bnx2x_update_eq_prod()
5231 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, in bnx2x_cnic_handle_cfc_del() argument
5236 if (!bp->cnic_eth_dev.starting_cid || in bnx2x_cnic_handle_cfc_del()
5237 (cid < bp->cnic_eth_dev.starting_cid && in bnx2x_cnic_handle_cfc_del()
5238 cid != bp->cnic_eth_dev.iscsi_l2_cid)) in bnx2x_cnic_handle_cfc_del()
5247 bnx2x_panic_dump(bp, false); in bnx2x_cnic_handle_cfc_del()
5249 bnx2x_cnic_cfc_comp(bp, cid, err); in bnx2x_cnic_handle_cfc_del()
5253 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) in bnx2x_handle_mcast_eqe() argument
5260 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_handle_mcast_eqe()
5262 netif_addr_lock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5265 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); in bnx2x_handle_mcast_eqe()
5268 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { in bnx2x_handle_mcast_eqe()
5269 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); in bnx2x_handle_mcast_eqe()
5275 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5278 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, in bnx2x_handle_classification_eqe() argument
5293 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) in bnx2x_handle_classification_eqe()
5294 vlan_mac_obj = &bp->iscsi_l2_mac_obj; in bnx2x_handle_classification_eqe()
5296 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; in bnx2x_handle_classification_eqe()
5301 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; in bnx2x_handle_classification_eqe()
5308 bnx2x_handle_mcast_eqe(bp); in bnx2x_handle_classification_eqe()
5316 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); in bnx2x_handle_classification_eqe()
5324 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5326 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) in bnx2x_handle_rx_mode_eqe() argument
5328 netif_addr_lock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5330 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_handle_rx_mode_eqe()
5333 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5334 bnx2x_set_storm_rx_mode(bp); in bnx2x_handle_rx_mode_eqe()
5336 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5337 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_handle_rx_mode_eqe()
5339 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5340 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_handle_rx_mode_eqe()
5342 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5345 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, in bnx2x_after_afex_vif_lists() argument
5352 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, in bnx2x_after_afex_vif_lists()
5357 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); in bnx2x_after_afex_vif_lists()
5362 static void bnx2x_after_function_update(struct bnx2x *bp) in bnx2x_after_function_update() argument
5381 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { in bnx2x_after_function_update()
5386 (bp->afex_def_vlan_tag & VLAN_VID_MASK); in bnx2x_after_function_update()
5390 for_each_eth_queue(bp, q) { in bnx2x_after_function_update()
5392 fp = &bp->fp[q]; in bnx2x_after_function_update()
5393 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5396 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5402 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { in bnx2x_after_function_update()
5403 fp = &bp->fp[FCOE_IDX(bp)]; in bnx2x_after_function_update()
5404 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5411 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_after_function_update()
5415 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5421 bnx2x_link_report(bp); in bnx2x_after_function_update()
5422 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_after_function_update()
5427 struct bnx2x *bp, u32 cid) in bnx2x_cid_to_q_obj() argument
5431 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) in bnx2x_cid_to_q_obj()
5432 return &bnx2x_fcoe_sp_obj(bp, q_obj); in bnx2x_cid_to_q_obj()
5434 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; in bnx2x_cid_to_q_obj()
5437 static void bnx2x_eq_int(struct bnx2x *bp) in bnx2x_eq_int() argument
5446 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; in bnx2x_eq_int()
5447 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; in bnx2x_eq_int()
5449 hw_cons = le16_to_cpu(*bp->eq_cons_sb); in bnx2x_eq_int()
5463 sw_cons = bp->eq_cons; in bnx2x_eq_int()
5464 sw_prod = bp->eq_prod; in bnx2x_eq_int()
5467 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); in bnx2x_eq_int()
5472 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; in bnx2x_eq_int()
5474 rc = bnx2x_iov_eq_sp_event(bp, elem); in bnx2x_eq_int()
5489 bnx2x_vf_mbx_schedule(bp, in bnx2x_eq_int()
5496 bp->stats_comp++); in bnx2x_eq_int()
5509 if (CNIC_LOADED(bp) && in bnx2x_eq_int()
5510 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) in bnx2x_eq_int()
5513 q_obj = bnx2x_cid_to_q_obj(bp, cid); in bnx2x_eq_int()
5515 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) in bnx2x_eq_int()
5522 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); in bnx2x_eq_int()
5523 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5530 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); in bnx2x_eq_int()
5531 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5542 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) in bnx2x_eq_int()
5550 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5557 bnx2x_schedule_sp_rtnl(bp, cmd, 0); in bnx2x_eq_int()
5563 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5565 bnx2x_after_afex_vif_lists(bp, elem); in bnx2x_eq_int()
5570 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) in bnx2x_eq_int()
5578 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) in bnx2x_eq_int()
5586 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5592 switch (opcode | bp->state) { in bnx2x_eq_int()
5617 bnx2x_handle_classification_eqe(bp, elem); in bnx2x_eq_int()
5627 bnx2x_handle_mcast_eqe(bp); in bnx2x_eq_int()
5637 bnx2x_handle_rx_mode_eqe(bp); in bnx2x_eq_int()
5642 elem->message.opcode, bp->state); in bnx2x_eq_int()
5649 atomic_add(spqe_cnt, &bp->eq_spq_left); in bnx2x_eq_int()
5651 bp->eq_cons = sw_cons; in bnx2x_eq_int()
5652 bp->eq_prod = sw_prod; in bnx2x_eq_int()
5657 bnx2x_update_eq_prod(bp, bp->eq_prod); in bnx2x_eq_int()
5662 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); in bnx2x_sp_task() local
5668 if (atomic_read(&bp->interrupt_occurred)) { in bnx2x_sp_task()
5671 u16 status = bnx2x_update_dsb_idx(bp); in bnx2x_sp_task()
5675 atomic_set(&bp->interrupt_occurred, 0); in bnx2x_sp_task()
5679 bnx2x_attn_int(bp); in bnx2x_sp_task()
5685 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_sp_task()
5687 if (FCOE_INIT(bp) && in bnx2x_sp_task()
5693 napi_schedule(&bnx2x_fcoe(bp, napi)); in bnx2x_sp_task()
5698 bnx2x_eq_int(bp); in bnx2x_sp_task()
5699 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, in bnx2x_sp_task()
5700 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); in bnx2x_sp_task()
5711 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, in bnx2x_sp_task()
5712 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); in bnx2x_sp_task()
5717 &bp->sp_state)) { in bnx2x_sp_task()
5718 bnx2x_link_report(bp); in bnx2x_sp_task()
5719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_sp_task()
5726 struct bnx2x *bp = netdev_priv(dev); in bnx2x_msix_sp_int() local
5728 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, in bnx2x_msix_sp_int()
5732 if (unlikely(bp->panic)) in bnx2x_msix_sp_int()
5736 if (CNIC_LOADED(bp)) { in bnx2x_msix_sp_int()
5740 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_msix_sp_int()
5742 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_msix_sp_int()
5749 bnx2x_schedule_sp_task(bp); in bnx2x_msix_sp_int()
5756 void bnx2x_drv_pulse(struct bnx2x *bp) in bnx2x_drv_pulse() argument
5758 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, in bnx2x_drv_pulse()
5759 bp->fw_drv_pulse_wr_seq); in bnx2x_drv_pulse()
5764 struct bnx2x *bp = (struct bnx2x *) data; in bnx2x_timer() local
5766 if (!netif_running(bp->dev)) in bnx2x_timer()
5769 if (IS_PF(bp) && in bnx2x_timer()
5770 !BP_NOMCP(bp)) { in bnx2x_timer()
5771 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_timer()
5775 ++bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5776 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; in bnx2x_timer()
5777 drv_pulse = bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5778 bnx2x_drv_pulse(bp); in bnx2x_timer()
5780 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & in bnx2x_timer()
5792 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_timer()
5793 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); in bnx2x_timer()
5796 if (IS_VF(bp)) in bnx2x_timer()
5797 bnx2x_timer_sriov(bp); in bnx2x_timer()
5799 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2x_timer()
5810 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) in bnx2x_fill() argument
5815 REG_WR(bp, addr + i, fill); in bnx2x_fill()
5818 REG_WR8(bp, addr + i, fill); in bnx2x_fill()
5822 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, in bnx2x_wr_fp_sb_data() argument
5829 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
5835 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) in bnx2x_zero_fp_sb() argument
5843 if (!CHIP_IS_E1x(bp)) { in bnx2x_zero_fp_sb()
5857 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_zero_fp_sb()
5859 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5862 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5868 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, in bnx2x_wr_sp_sb_data() argument
5871 int func = BP_FUNC(bp); in bnx2x_wr_sp_sb_data()
5874 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
5880 static void bnx2x_zero_sp_sb(struct bnx2x *bp) in bnx2x_zero_sp_sb() argument
5882 int func = BP_FUNC(bp); in bnx2x_zero_sp_sb()
5889 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_zero_sp_sb()
5891 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5894 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5937 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, in bnx2x_init_sb() argument
5948 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_init_sb()
5953 bnx2x_zero_fp_sb(bp, fw_sb_id); in bnx2x_init_sb()
5955 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_sb()
5958 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5961 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
5973 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5976 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
5994 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_init_sb()
5997 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, in bnx2x_update_coalesce_sb() argument
6000 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, in bnx2x_update_coalesce_sb()
6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6005 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6008 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6013 static void bnx2x_init_def_sb(struct bnx2x *bp) in bnx2x_init_def_sb() argument
6015 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_init_def_sb()
6016 dma_addr_t mapping = bp->def_status_blk_mapping; in bnx2x_init_def_sb()
6019 int port = BP_PORT(bp); in bnx2x_init_def_sb()
6020 int func = BP_FUNC(bp); in bnx2x_init_def_sb()
6027 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_def_sb()
6031 igu_sp_sb_index = bp->igu_dsb_id; in bnx2x_init_def_sb()
6040 bp->attn_state = 0; in bnx2x_init_def_sb()
6050 bp->attn_group[index].sig[sindex] = in bnx2x_init_def_sb()
6051 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); in bnx2x_init_def_sb()
6053 if (!CHIP_IS_E1x(bp)) in bnx2x_init_def_sb()
6059 bp->attn_group[index].sig[4] = REG_RD(bp, in bnx2x_init_def_sb()
6062 bp->attn_group[index].sig[4] = 0; in bnx2x_init_def_sb()
6065 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_def_sb()
6069 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
6070 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
6071 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_init_def_sb()
6072 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
6073 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
6079 bnx2x_zero_sp_sb(bp); in bnx2x_init_def_sb()
6088 sp_sb_data.p_func.vnic_id = BP_VN(bp); in bnx2x_init_def_sb()
6091 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_init_def_sb()
6093 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bnx2x_init_def_sb()
6096 void bnx2x_update_coalesce(struct bnx2x *bp) in bnx2x_update_coalesce() argument
6100 for_each_eth_queue(bp, i) in bnx2x_update_coalesce()
6101 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, in bnx2x_update_coalesce()
6102 bp->tx_ticks, bp->rx_ticks); in bnx2x_update_coalesce()
6105 static void bnx2x_init_sp_ring(struct bnx2x *bp) in bnx2x_init_sp_ring() argument
6107 spin_lock_init(&bp->spq_lock); in bnx2x_init_sp_ring()
6108 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); in bnx2x_init_sp_ring()
6110 bp->spq_prod_idx = 0; in bnx2x_init_sp_ring()
6111 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; in bnx2x_init_sp_ring()
6112 bp->spq_prod_bd = bp->spq; in bnx2x_init_sp_ring()
6113 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; in bnx2x_init_sp_ring()
6116 static void bnx2x_init_eq_ring(struct bnx2x *bp) in bnx2x_init_eq_ring() argument
6121 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; in bnx2x_init_eq_ring()
6124 cpu_to_le32(U64_HI(bp->eq_mapping + in bnx2x_init_eq_ring()
6127 cpu_to_le32(U64_LO(bp->eq_mapping + in bnx2x_init_eq_ring()
6130 bp->eq_cons = 0; in bnx2x_init_eq_ring()
6131 bp->eq_prod = NUM_EQ_DESC; in bnx2x_init_eq_ring()
6132 bp->eq_cons_sb = BNX2X_EQ_INDEX; in bnx2x_init_eq_ring()
6134 atomic_set(&bp->eq_spq_left, in bnx2x_init_eq_ring()
6139 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, in bnx2x_set_q_rx_mode() argument
6153 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; in bnx2x_set_q_rx_mode()
6154 ramrod_param.func_id = BP_FUNC(bp); in bnx2x_set_q_rx_mode()
6156 ramrod_param.pstate = &bp->sp_state; in bnx2x_set_q_rx_mode()
6159 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6160 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6162 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_set_q_rx_mode()
6170 rc = bnx2x_config_rx_mode(bp, &ramrod_param); in bnx2x_set_q_rx_mode()
6172 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); in bnx2x_set_q_rx_mode()
6179 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, in bnx2x_fill_accept_flags() argument
6204 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6220 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6240 if (IS_MF_SI(bp)) in bnx2x_fill_accept_flags()
6258 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) in bnx2x_set_storm_rx_mode() argument
6264 if (!NO_FCOE(bp)) in bnx2x_set_storm_rx_mode()
6268 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, in bnx2x_set_storm_rx_mode()
6276 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, in bnx2x_set_storm_rx_mode()
6281 static void bnx2x_init_internal_common(struct bnx2x *bp) in bnx2x_init_internal_common() argument
6288 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
6290 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_internal_common()
6291 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, in bnx2x_init_internal_common()
6292 CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_internal_common()
6297 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) in bnx2x_init_internal() argument
6302 bnx2x_init_internal_common(bp); in bnx2x_init_internal()
6322 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_igu_sb_id()
6327 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_fw_sb_id()
6332 if (CHIP_IS_E1x(fp->bp)) in bnx2x_fp_cl_id()
6333 return BP_L_ID(fp->bp) + fp->index; in bnx2x_fp_cl_id()
6338 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) in bnx2x_init_eth_fp() argument
6340 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; in bnx2x_init_eth_fp()
6366 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], in bnx2x_init_eth_fp()
6367 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), in bnx2x_init_eth_fp()
6368 FP_COS_TO_TXQ(fp, cos, bp), in bnx2x_init_eth_fp()
6374 if (IS_VF(bp)) in bnx2x_init_eth_fp()
6377 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, in bnx2x_init_eth_fp()
6380 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, in bnx2x_init_eth_fp()
6381 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_eth_fp()
6382 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_eth_fp()
6391 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_eth_fp()
6424 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) in bnx2x_init_tx_rings_cnic() argument
6428 for_each_tx_queue_cnic(bp, i) in bnx2x_init_tx_rings_cnic()
6429 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); in bnx2x_init_tx_rings_cnic()
6432 static void bnx2x_init_tx_rings(struct bnx2x *bp) in bnx2x_init_tx_rings() argument
6437 for_each_eth_queue(bp, i) in bnx2x_init_tx_rings()
6438 for_each_cos_in_tx_queue(&bp->fp[i], cos) in bnx2x_init_tx_rings()
6439 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); in bnx2x_init_tx_rings()
6442 static void bnx2x_init_fcoe_fp(struct bnx2x *bp) in bnx2x_init_fcoe_fp() argument
6444 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_init_fcoe_fp()
6447 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); in bnx2x_init_fcoe_fp()
6448 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, in bnx2x_init_fcoe_fp()
6450 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); in bnx2x_init_fcoe_fp()
6451 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; in bnx2x_init_fcoe_fp()
6452 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; in bnx2x_init_fcoe_fp()
6453 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; in bnx2x_init_fcoe_fp()
6454 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), in bnx2x_init_fcoe_fp()
6455 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, in bnx2x_init_fcoe_fp()
6461 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); in bnx2x_init_fcoe_fp()
6463 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = in bnx2x_init_fcoe_fp()
6473 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, in bnx2x_init_fcoe_fp()
6474 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_fcoe_fp()
6475 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_fcoe_fp()
6479 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_fcoe_fp()
6483 void bnx2x_nic_init_cnic(struct bnx2x *bp) in bnx2x_nic_init_cnic() argument
6485 if (!NO_FCOE(bp)) in bnx2x_nic_init_cnic()
6486 bnx2x_init_fcoe_fp(bp); in bnx2x_nic_init_cnic()
6488 bnx2x_init_sb(bp, bp->cnic_sb_mapping, in bnx2x_nic_init_cnic()
6490 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); in bnx2x_nic_init_cnic()
6494 bnx2x_init_rx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6495 bnx2x_init_tx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6502 void bnx2x_pre_irq_nic_init(struct bnx2x *bp) in bnx2x_pre_irq_nic_init() argument
6507 for_each_eth_queue(bp, i) in bnx2x_pre_irq_nic_init()
6508 bnx2x_init_eth_fp(bp, i); in bnx2x_pre_irq_nic_init()
6512 bnx2x_init_rx_rings(bp); in bnx2x_pre_irq_nic_init()
6513 bnx2x_init_tx_rings(bp); in bnx2x_pre_irq_nic_init()
6515 if (IS_PF(bp)) { in bnx2x_pre_irq_nic_init()
6517 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, in bnx2x_pre_irq_nic_init()
6518 bp->common.shmem_base, in bnx2x_pre_irq_nic_init()
6519 bp->common.shmem2_base, BP_PORT(bp)); in bnx2x_pre_irq_nic_init()
6522 bnx2x_init_def_sb(bp); in bnx2x_pre_irq_nic_init()
6523 bnx2x_update_dsb_idx(bp); in bnx2x_pre_irq_nic_init()
6524 bnx2x_init_sp_ring(bp); in bnx2x_pre_irq_nic_init()
6526 bnx2x_memset_stats(bp); in bnx2x_pre_irq_nic_init()
6530 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) in bnx2x_post_irq_nic_init() argument
6532 bnx2x_init_eq_ring(bp); in bnx2x_post_irq_nic_init()
6533 bnx2x_init_internal(bp, load_code); in bnx2x_post_irq_nic_init()
6534 bnx2x_pf_init(bp); in bnx2x_post_irq_nic_init()
6535 bnx2x_stats_init(bp); in bnx2x_post_irq_nic_init()
6541 bnx2x_int_enable(bp); in bnx2x_post_irq_nic_init()
6544 bnx2x_attn_int_deasserted0(bp, in bnx2x_post_irq_nic_init()
6545 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & in bnx2x_post_irq_nic_init()
6550 static int bnx2x_gunzip_init(struct bnx2x *bp) in bnx2x_gunzip_init() argument
6552 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, in bnx2x_gunzip_init()
6553 &bp->gunzip_mapping, GFP_KERNEL); in bnx2x_gunzip_init()
6554 if (bp->gunzip_buf == NULL) in bnx2x_gunzip_init()
6557 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); in bnx2x_gunzip_init()
6558 if (bp->strm == NULL) in bnx2x_gunzip_init()
6561 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); in bnx2x_gunzip_init()
6562 if (bp->strm->workspace == NULL) in bnx2x_gunzip_init()
6568 kfree(bp->strm); in bnx2x_gunzip_init()
6569 bp->strm = NULL; in bnx2x_gunzip_init()
6572 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_init()
6573 bp->gunzip_mapping); in bnx2x_gunzip_init()
6574 bp->gunzip_buf = NULL; in bnx2x_gunzip_init()
6581 static void bnx2x_gunzip_end(struct bnx2x *bp) in bnx2x_gunzip_end() argument
6583 if (bp->strm) { in bnx2x_gunzip_end()
6584 vfree(bp->strm->workspace); in bnx2x_gunzip_end()
6585 kfree(bp->strm); in bnx2x_gunzip_end()
6586 bp->strm = NULL; in bnx2x_gunzip_end()
6589 if (bp->gunzip_buf) { in bnx2x_gunzip_end()
6590 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_end()
6591 bp->gunzip_mapping); in bnx2x_gunzip_end()
6592 bp->gunzip_buf = NULL; in bnx2x_gunzip_end()
6596 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) in bnx2x_gunzip() argument
6613 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; in bnx2x_gunzip()
6614 bp->strm->avail_in = len - n; in bnx2x_gunzip()
6615 bp->strm->next_out = bp->gunzip_buf; in bnx2x_gunzip()
6616 bp->strm->avail_out = FW_BUF_SIZE; in bnx2x_gunzip()
6618 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); in bnx2x_gunzip()
6622 rc = zlib_inflate(bp->strm, Z_FINISH); in bnx2x_gunzip()
6624 netdev_err(bp->dev, "Firmware decompression error: %s\n", in bnx2x_gunzip()
6625 bp->strm->msg); in bnx2x_gunzip()
6627 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); in bnx2x_gunzip()
6628 if (bp->gunzip_outlen & 0x3) in bnx2x_gunzip()
6629 netdev_err(bp->dev, in bnx2x_gunzip()
6631 bp->gunzip_outlen); in bnx2x_gunzip()
6632 bp->gunzip_outlen >>= 2; in bnx2x_gunzip()
6634 zlib_inflateEnd(bp->strm); in bnx2x_gunzip()
6649 static void bnx2x_lb_pckt(struct bnx2x *bp) in bnx2x_lb_pckt() argument
6657 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6663 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6670 static int bnx2x_int_mem_test(struct bnx2x *bp) in bnx2x_int_mem_test() argument
6676 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_int_mem_test()
6678 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_int_mem_test()
6684 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6685 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6686 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6687 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6690 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6693 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6700 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6701 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6716 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6733 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6734 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6741 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6745 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6749 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6756 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6757 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6770 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6775 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6780 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6786 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); in bnx2x_int_mem_test()
6787 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); in bnx2x_int_mem_test()
6794 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6798 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6799 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6800 if (!CNIC_SUPPORT(bp)) in bnx2x_int_mem_test()
6802 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
6805 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6806 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6807 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6808 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6815 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) in bnx2x_enable_blocks_attention() argument
6819 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6820 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6824 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6825 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6832 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6833 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6834 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6835 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6836 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6837 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6840 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6841 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6842 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6845 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6846 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6847 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6848 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6855 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6858 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); in bnx2x_enable_blocks_attention()
6860 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6861 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6862 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6865 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6867 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6869 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6870 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6872 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6875 static void bnx2x_reset_common(struct bnx2x *bp) in bnx2x_reset_common() argument
6880 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
6883 if (CHIP_IS_E3(bp)) { in bnx2x_reset_common()
6888 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); in bnx2x_reset_common()
6891 static void bnx2x_setup_dmae(struct bnx2x *bp) in bnx2x_setup_dmae() argument
6893 bp->dmae_ready = 0; in bnx2x_setup_dmae()
6894 spin_lock_init(&bp->dmae_lock); in bnx2x_setup_dmae()
6897 static void bnx2x_init_pxp(struct bnx2x *bp) in bnx2x_init_pxp() argument
6902 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); in bnx2x_init_pxp()
6905 if (bp->mrrs == -1) in bnx2x_init_pxp()
6908 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); in bnx2x_init_pxp()
6909 r_order = bp->mrrs; in bnx2x_init_pxp()
6912 bnx2x_init_pxp_arb(bp, r_order, w_order); in bnx2x_init_pxp()
6915 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) in bnx2x_setup_fan_failure_detection() argument
6921 if (BP_NOMCP(bp)) in bnx2x_setup_fan_failure_detection()
6925 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & in bnx2x_setup_fan_failure_detection()
6940 bp, in bnx2x_setup_fan_failure_detection()
6941 bp->common.shmem_base, in bnx2x_setup_fan_failure_detection()
6942 bp->common.shmem2_base, in bnx2x_setup_fan_failure_detection()
6952 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); in bnx2x_setup_fan_failure_detection()
6955 val = REG_RD(bp, MISC_REG_SPIO_INT); in bnx2x_setup_fan_failure_detection()
6957 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
6960 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_setup_fan_failure_detection()
6962 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
6965 void bnx2x_pf_disable(struct bnx2x *bp) in bnx2x_pf_disable() argument
6967 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_pf_disable()
6970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
6971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
6975 static void bnx2x__common_init_phy(struct bnx2x *bp) in bnx2x__common_init_phy() argument
6979 if (SHMEM2_RD(bp, size) > in bnx2x__common_init_phy()
6980 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x__common_init_phy()
6982 shmem_base[0] = bp->common.shmem_base; in bnx2x__common_init_phy()
6983 shmem2_base[0] = bp->common.shmem2_base; in bnx2x__common_init_phy()
6984 if (!CHIP_IS_E1x(bp)) { in bnx2x__common_init_phy()
6986 SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x__common_init_phy()
6988 SHMEM2_RD(bp, other_shmem2_base_addr); in bnx2x__common_init_phy()
6990 bnx2x_acquire_phy_lock(bp); in bnx2x__common_init_phy()
6991 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, in bnx2x__common_init_phy()
6992 bp->common.chip_id); in bnx2x__common_init_phy()
6993 bnx2x_release_phy_lock(bp); in bnx2x__common_init_phy()
6996 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) in bnx2x_config_endianity() argument
6998 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); in bnx2x_config_endianity()
6999 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); in bnx2x_config_endianity()
7000 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); in bnx2x_config_endianity()
7001 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); in bnx2x_config_endianity()
7002 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); in bnx2x_config_endianity()
7005 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
7007 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); in bnx2x_config_endianity()
7008 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); in bnx2x_config_endianity()
7009 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); in bnx2x_config_endianity()
7010 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); in bnx2x_config_endianity()
7013 static void bnx2x_set_endianity(struct bnx2x *bp) in bnx2x_set_endianity() argument
7016 bnx2x_config_endianity(bp, 1); in bnx2x_set_endianity()
7018 bnx2x_config_endianity(bp, 0); in bnx2x_set_endianity()
7022 static void bnx2x_reset_endianity(struct bnx2x *bp) in bnx2x_reset_endianity() argument
7024 bnx2x_config_endianity(bp, 0); in bnx2x_reset_endianity()
7032 static int bnx2x_init_hw_common(struct bnx2x *bp) in bnx2x_init_hw_common() argument
7036 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7044 bnx2x_reset_common(bp); in bnx2x_init_hw_common()
7045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7048 if (CHIP_IS_E3(bp)) { in bnx2x_init_hw_common()
7052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); in bnx2x_init_hw_common()
7054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7056 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); in bnx2x_init_hw_common()
7058 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7068 for (abs_func_id = BP_PATH(bp); in bnx2x_init_hw_common()
7070 if (abs_func_id == BP_ABS_FUNC(bp)) { in bnx2x_init_hw_common()
7071 REG_WR(bp, in bnx2x_init_hw_common()
7077 bnx2x_pretend_func(bp, abs_func_id); in bnx2x_init_hw_common()
7079 bnx2x_pf_disable(bp); in bnx2x_init_hw_common()
7080 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7084 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); in bnx2x_init_hw_common()
7085 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7088 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7091 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); in bnx2x_init_hw_common()
7092 bnx2x_init_pxp(bp); in bnx2x_init_hw_common()
7093 bnx2x_set_endianity(bp); in bnx2x_init_hw_common()
7094 bnx2x_ilt_init_page_size(bp, INITOP_SET); in bnx2x_init_hw_common()
7096 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7097 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7102 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); in bnx2x_init_hw_common()
7107 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); in bnx2x_init_hw_common()
7118 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7202 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); in bnx2x_init_hw_common()
7203 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); in bnx2x_init_hw_common()
7204 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7206 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7207 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
7211 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7212 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7214 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7215 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : in bnx2x_init_hw_common()
7216 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); in bnx2x_init_hw_common()
7217 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); in bnx2x_init_hw_common()
7219 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); in bnx2x_init_hw_common()
7224 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); in bnx2x_init_hw_common()
7233 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); in bnx2x_init_hw_common()
7235 bnx2x_iov_init_dmae(bp); in bnx2x_init_hw_common()
7238 bp->dmae_ready = 1; in bnx2x_init_hw_common()
7239 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); in bnx2x_init_hw_common()
7241 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); in bnx2x_init_hw_common()
7243 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); in bnx2x_init_hw_common()
7245 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); in bnx2x_init_hw_common()
7247 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); in bnx2x_init_hw_common()
7249 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7250 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7251 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7252 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7254 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); in bnx2x_init_hw_common()
7257 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_common()
7260 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
7261 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7263 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_common()
7264 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); in bnx2x_init_hw_common()
7266 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); in bnx2x_init_hw_common()
7268 if (!CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7270 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7272 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_init_hw_common()
7274 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_init_hw_common()
7275 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7277 if (!CHIP_IS_E1(bp)) in bnx2x_init_hw_common()
7278 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7280 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_common()
7281 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7285 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7286 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7288 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7289 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7294 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7295 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7299 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7300 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7301 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); in bnx2x_init_hw_common()
7302 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7304 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7306 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7309 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7316 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7317 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); in bnx2x_init_hw_common()
7318 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7319 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7322 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
7327 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); in bnx2x_init_hw_common()
7328 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); in bnx2x_init_hw_common()
7329 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); in bnx2x_init_hw_common()
7331 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7332 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7336 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7337 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7339 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7340 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7342 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7343 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7347 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
7349 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); in bnx2x_init_hw_common()
7351 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_common()
7352 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7353 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7354 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7355 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7356 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7357 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7358 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7359 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7360 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7361 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7363 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7367 dev_alert(&bp->pdev->dev, in bnx2x_init_hw_common()
7371 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); in bnx2x_init_hw_common()
7373 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
7375 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); in bnx2x_init_hw_common()
7376 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7378 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7381 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7383 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); in bnx2x_init_hw_common()
7385 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) in bnx2x_init_hw_common()
7386 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7388 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); in bnx2x_init_hw_common()
7389 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); in bnx2x_init_hw_common()
7392 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7393 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7395 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7396 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
7399 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
7403 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
7409 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); in bnx2x_init_hw_common()
7410 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7412 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_common()
7413 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
7415 if (CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7417 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
7419 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7423 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7428 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7433 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7438 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7440 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7443 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_init_hw_common()
7444 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_init_hw_common()
7447 if ((val == 0) && bnx2x_int_mem_test(bp)) { in bnx2x_init_hw_common()
7453 bnx2x_setup_fan_failure_detection(bp); in bnx2x_init_hw_common()
7456 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); in bnx2x_init_hw_common()
7458 bnx2x_enable_blocks_attention(bp); in bnx2x_init_hw_common()
7459 bnx2x_enable_blocks_parity(bp); in bnx2x_init_hw_common()
7461 if (!BP_NOMCP(bp)) { in bnx2x_init_hw_common()
7462 if (CHIP_IS_E1x(bp)) in bnx2x_init_hw_common()
7463 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common()
7467 if (SHMEM2_HAS(bp, netproc_fw_ver)) in bnx2x_init_hw_common()
7468 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); in bnx2x_init_hw_common()
7478 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) in bnx2x_init_hw_common_chip() argument
7480 int rc = bnx2x_init_hw_common(bp); in bnx2x_init_hw_common_chip()
7486 if (!BP_NOMCP(bp)) in bnx2x_init_hw_common_chip()
7487 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common_chip()
7492 static int bnx2x_init_hw_port(struct bnx2x *bp) in bnx2x_init_hw_port() argument
7494 int port = BP_PORT(bp); in bnx2x_init_hw_port()
7501 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7503 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_port()
7504 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_port()
7505 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_port()
7512 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_port()
7513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
7515 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_port()
7516 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_port()
7517 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_port()
7518 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_port()
7520 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_port()
7521 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_port()
7522 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_port()
7523 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_port()
7526 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_port()
7528 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_port()
7529 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_port()
7530 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
7531 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
7534 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_port()
7536 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_port()
7538 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { in bnx2x_init_hw_port()
7540 if (IS_MF(bp)) in bnx2x_init_hw_port()
7541 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); in bnx2x_init_hw_port()
7542 else if (bp->dev->mtu > 4096) { in bnx2x_init_hw_port()
7543 if (bp->flags & ONE_PORT_FLAG) in bnx2x_init_hw_port()
7546 val = bp->dev->mtu; in bnx2x_init_hw_port()
7552 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); in bnx2x_init_hw_port()
7554 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
7555 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
7558 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_port()
7559 REG_WR(bp, (BP_PORT(bp) ? in bnx2x_init_hw_port()
7563 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_port()
7564 if (CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_port()
7565 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_port()
7567 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7570 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7573 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7581 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7584 (bp->path_has_ovlan ? 7 : 6)); in bnx2x_init_hw_port()
7588 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_port()
7589 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_port()
7590 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_port()
7591 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_port()
7593 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_port()
7594 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_port()
7595 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_port()
7596 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_port()
7598 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_port()
7599 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_port()
7601 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_port()
7603 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7605 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7608 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
7610 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7613 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7618 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_port()
7619 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_port()
7621 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_port()
7622 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_port()
7624 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7626 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7628 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_port()
7630 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_port()
7632 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_port()
7637 val = IS_MF(bp) ? 0xF7 : 0x7; in bnx2x_init_hw_port()
7639 val |= CHIP_IS_E1(bp) ? 0 : 0x10; in bnx2x_init_hw_port()
7640 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
7644 REG_WR(bp, reg, in bnx2x_init_hw_port()
7645 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7649 REG_WR(bp, reg, in bnx2x_init_hw_port()
7650 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7653 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_port()
7655 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7659 if (IS_MF_AFEX(bp)) in bnx2x_init_hw_port()
7660 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7664 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7667 IS_MF_SD(bp) ? 7 : 6); in bnx2x_init_hw_port()
7669 if (CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7670 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7672 NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_port()
7674 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7675 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
7677 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7679 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
7680 (IS_MF_SD(bp) ? 0x1 : 0x2)); in bnx2x_init_hw_port()
7682 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7684 switch (bp->mf_mode) { in bnx2x_init_hw_port()
7694 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
7698 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7699 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7700 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
7705 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_init_hw_port()
7709 val = REG_RD(bp, reg_addr); in bnx2x_init_hw_port()
7711 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
7717 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) in bnx2x_ilt_wr() argument
7722 if (CHIP_IS_E1(bp)) in bnx2x_ilt_wr()
7729 REG_WR_DMAE(bp, reg, wb_write, 2); in bnx2x_ilt_wr()
7732 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) in bnx2x_igu_clear_sb_gen() argument
7743 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_igu_clear_sb_gen()
7757 REG_WR(bp, igu_addr_data, data); in bnx2x_igu_clear_sb_gen()
7762 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_igu_clear_sb_gen()
7767 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) in bnx2x_igu_clear_sb_gen()
7770 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { in bnx2x_igu_clear_sb_gen()
7777 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) in bnx2x_igu_clear_sb() argument
7779 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); in bnx2x_igu_clear_sb()
7782 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) in bnx2x_clear_func_ilt() argument
7786 bnx2x_ilt_wr(bp, i, 0); in bnx2x_clear_func_ilt()
7789 static void bnx2x_init_searcher(struct bnx2x *bp) in bnx2x_init_searcher() argument
7791 int port = BP_PORT(bp); in bnx2x_init_searcher()
7792 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); in bnx2x_init_searcher()
7794 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_searcher()
7797 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) in bnx2x_func_switch_update() argument
7808 func_params.f_obj = &bp->func_obj; in bnx2x_func_switch_update()
7818 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_switch_update()
7823 static int bnx2x_reset_nic_mode(struct bnx2x *bp) in bnx2x_reset_nic_mode() argument
7825 int rc, i, port = BP_PORT(bp); in bnx2x_reset_nic_mode()
7829 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7830 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_reset_nic_mode()
7832 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7834 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7837 mac_en[i] = REG_RD(bp, port ? in bnx2x_reset_nic_mode()
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7849 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7857 rc = bnx2x_func_switch_update(bp, 1); in bnx2x_reset_nic_mode()
7864 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7867 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7868 bnx2x_set_rx_filter(&bp->link_params, 1); in bnx2x_reset_nic_mode()
7870 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7873 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7881 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7885 rc = bnx2x_func_switch_update(bp, 0); in bnx2x_reset_nic_mode()
7895 int bnx2x_init_hw_func_cnic(struct bnx2x *bp) in bnx2x_init_hw_func_cnic() argument
7899 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); in bnx2x_init_hw_func_cnic()
7901 if (CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func_cnic()
7903 bnx2x_init_searcher(bp); in bnx2x_init_hw_func_cnic()
7906 rc = bnx2x_reset_nic_mode(bp); in bnx2x_init_hw_func_cnic()
7922 static void bnx2x_clean_pglue_errors(struct bnx2x *bp) in bnx2x_clean_pglue_errors() argument
7924 if (!CHIP_IS_E1x(bp)) in bnx2x_clean_pglue_errors()
7925 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, in bnx2x_clean_pglue_errors()
7926 1 << BP_ABS_FUNC(bp)); in bnx2x_clean_pglue_errors()
7929 static int bnx2x_init_hw_func(struct bnx2x *bp) in bnx2x_init_hw_func() argument
7931 int port = BP_PORT(bp); in bnx2x_init_hw_func()
7932 int func = BP_FUNC(bp); in bnx2x_init_hw_func()
7934 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7943 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7944 rc = bnx2x_pf_flr_clnup(bp); in bnx2x_init_hw_func()
7946 bnx2x_fw_dump(bp); in bnx2x_init_hw_func()
7952 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
7954 val = REG_RD(bp, addr); in bnx2x_init_hw_func()
7956 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
7959 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_func()
7960 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_func()
7962 ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7965 if (IS_SRIOV(bp)) in bnx2x_init_hw_func()
7967 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); in bnx2x_init_hw_func()
7973 for (i = 0; i < L2_ILT_LINES(bp); i++) { in bnx2x_init_hw_func()
7974 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; in bnx2x_init_hw_func()
7976 bp->context[i].cxt_mapping; in bnx2x_init_hw_func()
7977 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; in bnx2x_init_hw_func()
7980 bnx2x_ilt_init_op(bp, INITOP_SET); in bnx2x_init_hw_func()
7982 if (!CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func()
7983 bnx2x_init_searcher(bp); in bnx2x_init_hw_func()
7984 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
7988 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
7992 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7998 if (!(bp->flags & USING_MSIX_FLAG)) in bnx2x_init_hw_func()
8012 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
8014 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
8017 bp->dmae_ready = 1; in bnx2x_init_hw_func()
8019 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_func()
8021 bnx2x_clean_pglue_errors(bp); in bnx2x_init_hw_func()
8023 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_func()
8024 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_func()
8025 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_func()
8026 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_func()
8027 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_func()
8028 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_func()
8029 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_func()
8030 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_func()
8031 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_func()
8032 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_func()
8033 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_func()
8034 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_func()
8035 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_func()
8037 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8038 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
8040 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8041 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8042 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8043 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8044 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8046 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_func()
8048 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_func()
8049 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_func()
8050 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ in bnx2x_init_hw_func()
8052 bnx2x_iov_init_dq(bp); in bnx2x_init_hw_func()
8054 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_func()
8055 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_func()
8056 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_func()
8057 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_func()
8058 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_func()
8059 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_func()
8060 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_func()
8061 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_func()
8062 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_func()
8063 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8064 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8066 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_func()
8068 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_func()
8070 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8071 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
8073 if (IS_MF(bp)) { in bnx2x_init_hw_func()
8074 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { in bnx2x_init_hw_func()
8075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_init_hw_func()
8076 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, in bnx2x_init_hw_func()
8077 bp->mf_ov); in bnx2x_init_hw_func()
8081 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_func()
8084 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
8085 if (CHIP_IS_E1H(bp)) { in bnx2x_init_hw_func()
8086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8091 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_func()
8096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8098 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8099 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8100 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8103 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_func()
8105 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8128 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8130 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { in bnx2x_init_hw_func()
8131 prod_offset = (bp->igu_base_sb + sb_idx) * in bnx2x_init_hw_func()
8137 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8140 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, in bnx2x_init_hw_func()
8142 bnx2x_igu_clear_sb(bp, in bnx2x_init_hw_func()
8143 bp->igu_base_sb + sb_idx); in bnx2x_init_hw_func()
8147 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8150 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_func()
8151 dsb_idx = BP_FUNC(bp); in bnx2x_init_hw_func()
8153 dsb_idx = BP_VN(bp); in bnx2x_init_hw_func()
8155 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8167 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8170 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_hw_func()
8171 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8182 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8187 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); in bnx2x_init_hw_func()
8191 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8192 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8193 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8194 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8195 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8196 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8201 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8202 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8204 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8207 BP_PORT(bp) * (main_mem_size * 4); in bnx2x_init_hw_func()
8211 val = REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8221 bnx2x_read_dmae(bp, i, main_mem_width / 4); in bnx2x_init_hw_func()
8222 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), in bnx2x_init_hw_func()
8226 REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8231 REG_WR8(bp, BAR_USTRORM_INTMEM + in bnx2x_init_hw_func()
8232 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8233 REG_WR8(bp, BAR_TSTRORM_INTMEM + in bnx2x_init_hw_func()
8234 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8235 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_init_hw_func()
8236 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8237 REG_WR8(bp, BAR_XSTRORM_INTMEM + in bnx2x_init_hw_func()
8238 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8241 bnx2x_phy_probe(&bp->link_params); in bnx2x_init_hw_func()
8246 void bnx2x_free_mem_cnic(struct bnx2x *bp) in bnx2x_free_mem_cnic() argument
8248 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); in bnx2x_free_mem_cnic()
8250 if (!CHIP_IS_E1x(bp)) in bnx2x_free_mem_cnic()
8251 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8254 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8257 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem_cnic()
8260 void bnx2x_free_mem(struct bnx2x *bp) in bnx2x_free_mem() argument
8264 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, in bnx2x_free_mem()
8265 bp->fw_stats_data_sz + bp->fw_stats_req_sz); in bnx2x_free_mem()
8267 if (IS_VF(bp)) in bnx2x_free_mem()
8270 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, in bnx2x_free_mem()
8273 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, in bnx2x_free_mem()
8276 for (i = 0; i < L2_ILT_LINES(bp); i++) in bnx2x_free_mem()
8277 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, in bnx2x_free_mem()
8278 bp->context[i].size); in bnx2x_free_mem()
8279 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); in bnx2x_free_mem()
8281 BNX2X_FREE(bp->ilt->lines); in bnx2x_free_mem()
8283 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_free_mem()
8285 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, in bnx2x_free_mem()
8288 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem()
8290 bnx2x_iov_free_mem(bp); in bnx2x_free_mem()
8293 int bnx2x_alloc_mem_cnic(struct bnx2x *bp) in bnx2x_alloc_mem_cnic() argument
8295 if (!CHIP_IS_E1x(bp)) { in bnx2x_alloc_mem_cnic()
8297 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8299 if (!bp->cnic_sb.e2_sb) in bnx2x_alloc_mem_cnic()
8302 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8304 if (!bp->cnic_sb.e1x_sb) in bnx2x_alloc_mem_cnic()
8308 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem_cnic()
8310 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem_cnic()
8311 if (!bp->t2) in bnx2x_alloc_mem_cnic()
8316 bp->cnic_eth_dev.addr_drv_info_to_mcp = in bnx2x_alloc_mem_cnic()
8317 &bp->slowpath->drv_info_to_mcp; in bnx2x_alloc_mem_cnic()
8319 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem_cnic()
8325 bnx2x_free_mem_cnic(bp); in bnx2x_alloc_mem_cnic()
8330 int bnx2x_alloc_mem(struct bnx2x *bp) in bnx2x_alloc_mem() argument
8334 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem()
8336 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem()
8337 if (!bp->t2) in bnx2x_alloc_mem()
8341 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, in bnx2x_alloc_mem()
8343 if (!bp->def_status_blk) in bnx2x_alloc_mem()
8346 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, in bnx2x_alloc_mem()
8348 if (!bp->slowpath) in bnx2x_alloc_mem()
8364 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); in bnx2x_alloc_mem()
8367 bp->context[i].size = min(CDU_ILT_PAGE_SZ, in bnx2x_alloc_mem()
8369 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, in bnx2x_alloc_mem()
8370 bp->context[i].size); in bnx2x_alloc_mem()
8371 if (!bp->context[i].vcxt) in bnx2x_alloc_mem()
8373 allocated += bp->context[i].size; in bnx2x_alloc_mem()
8375 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), in bnx2x_alloc_mem()
8377 if (!bp->ilt->lines) in bnx2x_alloc_mem()
8380 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem()
8383 if (bnx2x_iov_alloc_mem(bp)) in bnx2x_alloc_mem()
8387 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_alloc_mem()
8388 if (!bp->spq) in bnx2x_alloc_mem()
8392 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, in bnx2x_alloc_mem()
8394 if (!bp->eq_ring) in bnx2x_alloc_mem()
8400 bnx2x_free_mem(bp); in bnx2x_alloc_mem()
8409 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, in bnx2x_set_mac_one() argument
8435 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); in bnx2x_set_mac_one()
8447 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, in bnx2x_set_vlan_one() argument
8470 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); in bnx2x_set_vlan_one()
8483 int bnx2x_del_all_macs(struct bnx2x *bp, in bnx2x_del_all_macs() argument
8497 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); in bnx2x_del_all_macs()
8504 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) in bnx2x_set_eth_mac() argument
8506 if (IS_PF(bp)) { in bnx2x_set_eth_mac()
8511 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8512 &bp->sp_objs->mac_obj, set, in bnx2x_set_eth_mac()
8515 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8516 bp->fp->index, set); in bnx2x_set_eth_mac()
8520 int bnx2x_setup_leading(struct bnx2x *bp) in bnx2x_setup_leading() argument
8522 if (IS_PF(bp)) in bnx2x_setup_leading()
8523 return bnx2x_setup_queue(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8525 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8535 int bnx2x_set_int_mode(struct bnx2x *bp) in bnx2x_set_int_mode() argument
8539 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { in bnx2x_set_int_mode()
8547 rc = bnx2x_enable_msix(bp); in bnx2x_set_int_mode()
8554 if (rc && IS_VF(bp)) in bnx2x_set_int_mode()
8559 bp->num_queues, in bnx2x_set_int_mode()
8560 1 + bp->num_cnic_queues); in bnx2x_set_int_mode()
8564 bnx2x_enable_msi(bp); in bnx2x_set_int_mode()
8568 bp->num_ethernet_queues = 1; in bnx2x_set_int_mode()
8569 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; in bnx2x_set_int_mode()
8580 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) in bnx2x_cid_ilt_lines() argument
8582 if (IS_SRIOV(bp)) in bnx2x_cid_ilt_lines()
8584 return L2_ILT_LINES(bp); in bnx2x_cid_ilt_lines()
8587 void bnx2x_ilt_set_info(struct bnx2x *bp) in bnx2x_ilt_set_info() argument
8590 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_set_info()
8593 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); in bnx2x_ilt_set_info()
8602 line += bnx2x_cid_ilt_lines(bp); in bnx2x_ilt_set_info()
8604 if (CNIC_SUPPORT(bp)) in bnx2x_ilt_set_info()
8616 if (QM_INIT(bp->qm_cid_count)) { in bnx2x_ilt_set_info()
8624 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, in bnx2x_ilt_set_info()
8638 if (CNIC_SUPPORT(bp)) { in bnx2x_ilt_set_info()
8688 static void bnx2x_pf_q_prep_init(struct bnx2x *bp, in bnx2x_pf_q_prep_init() argument
8706 init_params->rx.hc_rate = bp->rx_ticks ? in bnx2x_pf_q_prep_init()
8707 (1000000 / bp->rx_ticks) : 0; in bnx2x_pf_q_prep_init()
8708 init_params->tx.hc_rate = bp->tx_ticks ? in bnx2x_pf_q_prep_init()
8709 (1000000 / bp->tx_ticks) : 0; in bnx2x_pf_q_prep_init()
8735 &bp->context[cxt_index].vcxt[cxt_offset].eth; in bnx2x_pf_q_prep_init()
8739 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_tx_only() argument
8750 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); in bnx2x_setup_tx_only()
8756 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); in bnx2x_setup_tx_only()
8759 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); in bnx2x_setup_tx_only()
8768 return bnx2x_queue_state_change(bp, q_params); in bnx2x_setup_tx_only()
8782 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_queue() argument
8797 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, in bnx2x_setup_queue()
8800 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_setup_queue()
8805 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); in bnx2x_setup_queue()
8811 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8823 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); in bnx2x_setup_queue()
8826 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, in bnx2x_setup_queue()
8829 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, in bnx2x_setup_queue()
8832 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, in bnx2x_setup_queue()
8839 bp->fcoe_init = true; in bnx2x_setup_queue()
8842 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8854 rc = bnx2x_setup_tx_only(bp, fp, &q_params, in bnx2x_setup_queue()
8866 static int bnx2x_stop_queue(struct bnx2x *bp, int index) in bnx2x_stop_queue() argument
8868 struct bnx2x_fastpath *fp = &bp->fp[index]; in bnx2x_stop_queue()
8875 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_stop_queue()
8896 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8905 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8912 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8921 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8929 return bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8932 static void bnx2x_reset_func(struct bnx2x *bp) in bnx2x_reset_func() argument
8934 int port = BP_PORT(bp); in bnx2x_reset_func()
8935 int func = BP_FUNC(bp); in bnx2x_reset_func()
8939 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8940 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8941 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8942 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8945 for_each_eth_queue(bp, i) { in bnx2x_reset_func()
8946 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_reset_func()
8947 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8952 if (CNIC_LOADED(bp)) in bnx2x_reset_func()
8954 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8956 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); in bnx2x_reset_func()
8959 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8964 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
8968 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_reset_func()
8969 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8970 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8972 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
8973 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
8976 if (CNIC_LOADED(bp)) { in bnx2x_reset_func()
8978 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
8985 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) in bnx2x_reset_func()
8990 bnx2x_clear_func_ilt(bp, func); in bnx2x_reset_func()
8995 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { in bnx2x_reset_func()
9003 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); in bnx2x_reset_func()
9007 if (!CHIP_IS_E1x(bp)) in bnx2x_reset_func()
9008 bnx2x_pf_disable(bp); in bnx2x_reset_func()
9010 bp->dmae_ready = 0; in bnx2x_reset_func()
9013 static void bnx2x_reset_port(struct bnx2x *bp) in bnx2x_reset_port() argument
9015 int port = BP_PORT(bp); in bnx2x_reset_port()
9019 bnx2x__link_reset(bp); in bnx2x_reset_port()
9021 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
9024 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
9026 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
9030 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
9034 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); in bnx2x_reset_port()
9042 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) in bnx2x_reset_hw() argument
9049 func_params.f_obj = &bp->func_obj; in bnx2x_reset_hw()
9054 return bnx2x_func_state_change(bp, &func_params); in bnx2x_reset_hw()
9057 static int bnx2x_func_stop(struct bnx2x *bp) in bnx2x_func_stop() argument
9064 func_params.f_obj = &bp->func_obj; in bnx2x_func_stop()
9073 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
9080 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
9095 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) in bnx2x_send_unload_req() argument
9098 int port = BP_PORT(bp); in bnx2x_send_unload_req()
9104 else if (bp->flags & NO_WOL_FLAG) in bnx2x_send_unload_req()
9107 else if (bp->wol) { in bnx2x_send_unload_req()
9109 u8 *mac_addr = bp->dev->dev_addr; in bnx2x_send_unload_req()
9110 struct pci_dev *pdev = bp->pdev; in bnx2x_send_unload_req()
9117 u8 entry = (BP_VN(bp) + 1)*8; in bnx2x_send_unload_req()
9120 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); in bnx2x_send_unload_req()
9124 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); in bnx2x_send_unload_req()
9137 if (!BP_NOMCP(bp)) in bnx2x_send_unload_req()
9138 reset_code = bnx2x_fw_command(bp, reset_code, 0); in bnx2x_send_unload_req()
9140 int path = BP_PATH(bp); in bnx2x_send_unload_req()
9167 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) in bnx2x_send_unload_done() argument
9172 if (!BP_NOMCP(bp)) in bnx2x_send_unload_done()
9173 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); in bnx2x_send_unload_done()
9176 static int bnx2x_func_wait_started(struct bnx2x *bp) in bnx2x_func_wait_started() argument
9179 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_func_wait_started()
9181 if (!bp->port.pmf) in bnx2x_func_wait_started()
9200 synchronize_irq(bp->msix_table[0].vector); in bnx2x_func_wait_started()
9202 synchronize_irq(bp->pdev->irq); in bnx2x_func_wait_started()
9207 while (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9211 if (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9226 func_params.f_obj = &bp->func_obj; in bnx2x_func_wait_started()
9232 bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9236 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9243 static void bnx2x_disable_ptp(struct bnx2x *bp) in bnx2x_disable_ptp() argument
9245 int port = BP_PORT(bp); in bnx2x_disable_ptp()
9248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_disable_ptp()
9252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9256 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9262 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_disable_ptp()
9267 static void bnx2x_stop_ptp(struct bnx2x *bp) in bnx2x_stop_ptp() argument
9272 cancel_work_sync(&bp->ptp_task); in bnx2x_stop_ptp()
9274 if (bp->ptp_tx_skb) { in bnx2x_stop_ptp()
9275 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_stop_ptp()
9276 bp->ptp_tx_skb = NULL; in bnx2x_stop_ptp()
9280 bnx2x_disable_ptp(bp); in bnx2x_stop_ptp()
9285 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) in bnx2x_chip_cleanup() argument
9287 int port = BP_PORT(bp); in bnx2x_chip_cleanup()
9294 for_each_tx_queue(bp, i) { in bnx2x_chip_cleanup()
9295 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_chip_cleanup()
9298 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); in bnx2x_chip_cleanup()
9309 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, in bnx2x_chip_cleanup()
9315 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, in bnx2x_chip_cleanup()
9322 if (!CHIP_IS_E1(bp)) in bnx2x_chip_cleanup()
9323 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9329 netif_addr_lock_bh(bp->dev); in bnx2x_chip_cleanup()
9331 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_chip_cleanup()
9332 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_chip_cleanup()
9334 bnx2x_set_storm_rx_mode(bp); in bnx2x_chip_cleanup()
9337 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_chip_cleanup()
9338 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_chip_cleanup()
9342 netif_addr_unlock_bh(bp->dev); in bnx2x_chip_cleanup()
9344 bnx2x_iov_chip_cleanup(bp); in bnx2x_chip_cleanup()
9351 reset_code = bnx2x_send_unload_req(bp, unload_mode); in bnx2x_chip_cleanup()
9357 rc = bnx2x_func_wait_started(bp); in bnx2x_chip_cleanup()
9368 for_each_eth_queue(bp, i) in bnx2x_chip_cleanup()
9369 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9376 if (CNIC_LOADED(bp)) { in bnx2x_chip_cleanup()
9377 for_each_cnic_queue(bp, i) in bnx2x_chip_cleanup()
9378 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9389 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) in bnx2x_chip_cleanup()
9395 rc = bnx2x_func_stop(bp); in bnx2x_chip_cleanup()
9408 if (bp->flags & PTP_SUPPORTED) in bnx2x_chip_cleanup()
9409 bnx2x_stop_ptp(bp); in bnx2x_chip_cleanup()
9412 bnx2x_netif_stop(bp, 1); in bnx2x_chip_cleanup()
9414 bnx2x_del_all_napi(bp); in bnx2x_chip_cleanup()
9415 if (CNIC_LOADED(bp)) in bnx2x_chip_cleanup()
9416 bnx2x_del_all_napi_cnic(bp); in bnx2x_chip_cleanup()
9419 bnx2x_free_irq(bp); in bnx2x_chip_cleanup()
9422 rc = bnx2x_reset_hw(bp, reset_code); in bnx2x_chip_cleanup()
9427 bnx2x_send_unload_done(bp, keep_link); in bnx2x_chip_cleanup()
9430 void bnx2x_disable_close_the_gate(struct bnx2x *bp) in bnx2x_disable_close_the_gate() argument
9436 if (CHIP_IS_E1(bp)) { in bnx2x_disable_close_the_gate()
9437 int port = BP_PORT(bp); in bnx2x_disable_close_the_gate()
9441 val = REG_RD(bp, addr); in bnx2x_disable_close_the_gate()
9443 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
9445 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); in bnx2x_disable_close_the_gate()
9448 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
9453 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) in bnx2x_set_234_gates() argument
9458 if (!CHIP_IS_E1(bp)) { in bnx2x_set_234_gates()
9460 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bnx2x_set_234_gates()
9462 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bnx2x_set_234_gates()
9466 if (CHIP_IS_E1x(bp)) { in bnx2x_set_234_gates()
9468 val = REG_RD(bp, HC_REG_CONFIG_1); in bnx2x_set_234_gates()
9469 REG_WR(bp, HC_REG_CONFIG_1, in bnx2x_set_234_gates()
9473 val = REG_RD(bp, HC_REG_CONFIG_0); in bnx2x_set_234_gates()
9474 REG_WR(bp, HC_REG_CONFIG_0, in bnx2x_set_234_gates()
9479 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_set_234_gates()
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, in bnx2x_set_234_gates()
9494 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_clp_reset_prep() argument
9497 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_prep()
9499 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); in bnx2x_clp_reset_prep()
9508 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) in bnx2x_clp_reset_done() argument
9511 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_done()
9512 MF_CFG_WR(bp, shared_mf_config.clp_mb, in bnx2x_clp_reset_done()
9524 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_reset_mcp_prep() argument
9532 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_prep()
9533 bnx2x_clp_reset_prep(bp, magic_val); in bnx2x_reset_mcp_prep()
9536 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_reset_mcp_prep()
9538 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); in bnx2x_reset_mcp_prep()
9542 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9553 static void bnx2x_mcp_wait_one(struct bnx2x *bp) in bnx2x_mcp_wait_one() argument
9557 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_mcp_wait_one()
9566 static int bnx2x_init_shmem(struct bnx2x *bp) in bnx2x_init_shmem() argument
9572 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_init_shmem()
9573 if (bp->common.shmem_base) { in bnx2x_init_shmem()
9574 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); in bnx2x_init_shmem()
9579 bnx2x_mcp_wait_one(bp); in bnx2x_init_shmem()
9588 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) in bnx2x_reset_mcp_comp() argument
9590 int rc = bnx2x_init_shmem(bp); in bnx2x_reset_mcp_comp()
9593 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_comp()
9594 bnx2x_clp_reset_done(bp, magic_val); in bnx2x_reset_mcp_comp()
9599 static void bnx2x_pxp_prep(struct bnx2x *bp) in bnx2x_pxp_prep() argument
9601 if (!CHIP_IS_E1(bp)) { in bnx2x_pxp_prep()
9602 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9603 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9618 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) in bnx2x_process_kill_chip_reset() argument
9670 if (CHIP_IS_E1(bp)) in bnx2x_process_kill_chip_reset()
9672 else if (CHIP_IS_E1H(bp)) in bnx2x_process_kill_chip_reset()
9674 else if (CHIP_IS_E2(bp)) in bnx2x_process_kill_chip_reset()
9697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
9700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
9706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_process_kill_chip_reset()
9712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
9725 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) in bnx2x_er_poll_igu_vq() argument
9731 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); in bnx2x_er_poll_igu_vq()
9748 static int bnx2x_process_kill(struct bnx2x *bp, bool global) in bnx2x_process_kill() argument
9757 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); in bnx2x_process_kill()
9758 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); in bnx2x_process_kill()
9759 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); in bnx2x_process_kill()
9760 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); in bnx2x_process_kill()
9761 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); in bnx2x_process_kill()
9762 if (CHIP_IS_E3(bp)) in bnx2x_process_kill()
9763 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); in bnx2x_process_kill()
9769 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) in bnx2x_process_kill()
9785 bnx2x_set_234_gates(bp, true); in bnx2x_process_kill()
9788 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) in bnx2x_process_kill()
9794 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9808 bnx2x_reset_mcp_prep(bp, &val); in bnx2x_process_kill()
9811 bnx2x_pxp_prep(bp); in bnx2x_process_kill()
9815 bnx2x_process_kill_chip_reset(bp, global); in bnx2x_process_kill()
9819 if (!CHIP_IS_E1x(bp)) in bnx2x_process_kill()
9820 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
9824 if (global && bnx2x_reset_mcp_comp(bp, val)) in bnx2x_process_kill()
9830 bnx2x_set_234_gates(bp, false); in bnx2x_process_kill()
9838 static int bnx2x_leader_reset(struct bnx2x *bp) in bnx2x_leader_reset() argument
9841 bool global = bnx2x_reset_is_global(bp); in bnx2x_leader_reset()
9847 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9848 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, in bnx2x_leader_reset()
9861 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); in bnx2x_leader_reset()
9870 if (bnx2x_process_kill(bp, global)) { in bnx2x_leader_reset()
9872 BP_PATH(bp)); in bnx2x_leader_reset()
9881 bnx2x_set_reset_done(bp); in bnx2x_leader_reset()
9883 bnx2x_clear_reset_global(bp); in bnx2x_leader_reset()
9887 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9888 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bnx2x_leader_reset()
9889 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); in bnx2x_leader_reset()
9892 bp->is_leader = 0; in bnx2x_leader_reset()
9893 bnx2x_release_leader_lock(bp); in bnx2x_leader_reset()
9898 static void bnx2x_recovery_failed(struct bnx2x *bp) in bnx2x_recovery_failed() argument
9900 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); in bnx2x_recovery_failed()
9903 netif_device_detach(bp->dev); in bnx2x_recovery_failed()
9909 bnx2x_set_reset_in_progress(bp); in bnx2x_recovery_failed()
9912 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_recovery_failed()
9914 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_recovery_failed()
9924 static void bnx2x_parity_recover(struct bnx2x *bp) in bnx2x_parity_recover() argument
9932 switch (bp->recovery_state) { in bnx2x_parity_recover()
9935 is_parity = bnx2x_chk_parity_attn(bp, &global, false); in bnx2x_parity_recover()
9939 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
9940 bnx2x_set_reset_in_progress(bp); in bnx2x_parity_recover()
9948 bnx2x_set_reset_global(bp); in bnx2x_parity_recover()
9950 bp->is_leader = 1; in bnx2x_parity_recover()
9955 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) in bnx2x_parity_recover()
9958 bp->recovery_state = BNX2X_RECOVERY_WAIT; in bnx2x_parity_recover()
9969 if (bp->is_leader) { in bnx2x_parity_recover()
9970 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_parity_recover()
9972 bnx2x_get_load_status(bp, other_engine); in bnx2x_parity_recover()
9974 bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_parity_recover()
9975 global = bnx2x_reset_is_global(bp); in bnx2x_parity_recover()
9990 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
9999 if (bnx2x_leader_reset(bp)) { in bnx2x_parity_recover()
10000 bnx2x_recovery_failed(bp); in bnx2x_parity_recover()
10012 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { in bnx2x_parity_recover()
10019 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
10023 bp->is_leader = 1; in bnx2x_parity_recover()
10027 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
10036 if (bnx2x_reset_is_global(bp)) { in bnx2x_parity_recover()
10038 &bp->sp_rtnl_task, in bnx2x_parity_recover()
10044 bp->eth_stats.recoverable_error; in bnx2x_parity_recover()
10046 bp->eth_stats.unrecoverable_error; in bnx2x_parity_recover()
10047 bp->recovery_state = in bnx2x_parity_recover()
10049 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { in bnx2x_parity_recover()
10051 netdev_err(bp->dev, in bnx2x_parity_recover()
10054 netif_device_detach(bp->dev); in bnx2x_parity_recover()
10057 bp, PCI_D3hot); in bnx2x_parity_recover()
10060 bp->recovery_state = in bnx2x_parity_recover()
10065 bp->eth_stats.recoverable_error = in bnx2x_parity_recover()
10067 bp->eth_stats.unrecoverable_error = in bnx2x_parity_recover()
10080 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port) in bnx2x_vxlan_port_update() argument
10092 func_params.f_obj = &bp->func_obj; in bnx2x_vxlan_port_update()
10099 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_vxlan_port_update()
10106 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port) in __bnx2x_add_vxlan_port() argument
10108 if (!netif_running(bp->dev)) in __bnx2x_add_vxlan_port()
10111 if (bp->vxlan_dst_port_count && bp->vxlan_dst_port == port) { in __bnx2x_add_vxlan_port()
10112 bp->vxlan_dst_port_count++; in __bnx2x_add_vxlan_port()
10116 if (bp->vxlan_dst_port_count || !IS_PF(bp)) { in __bnx2x_add_vxlan_port()
10121 bp->vxlan_dst_port = port; in __bnx2x_add_vxlan_port()
10122 bp->vxlan_dst_port_count = 1; in __bnx2x_add_vxlan_port()
10123 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0); in __bnx2x_add_vxlan_port()
10129 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_add_vxlan_port() local
10132 __bnx2x_add_vxlan_port(bp, t_port); in bnx2x_add_vxlan_port()
10135 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port) in __bnx2x_del_vxlan_port() argument
10137 if (!bp->vxlan_dst_port_count || bp->vxlan_dst_port != port || in __bnx2x_del_vxlan_port()
10138 !IS_PF(bp)) { in __bnx2x_del_vxlan_port()
10142 bp->vxlan_dst_port_count--; in __bnx2x_del_vxlan_port()
10143 if (bp->vxlan_dst_port_count) in __bnx2x_del_vxlan_port()
10146 if (netif_running(bp->dev)) { in __bnx2x_del_vxlan_port()
10147 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0); in __bnx2x_del_vxlan_port()
10149 bp->vxlan_dst_port = 0; in __bnx2x_del_vxlan_port()
10150 netdev_info(bp->dev, "Deleted vxlan dest port %d", port); in __bnx2x_del_vxlan_port()
10157 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_del_vxlan_port() local
10160 __bnx2x_del_vxlan_port(bp, t_port); in bnx2x_del_vxlan_port()
10171 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); in bnx2x_sp_rtnl_task() local
10178 if (!netif_running(bp->dev)) { in bnx2x_sp_rtnl_task()
10183 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { in bnx2x_sp_rtnl_task()
10193 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10196 bnx2x_parity_recover(bp); in bnx2x_sp_rtnl_task()
10202 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10213 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10216 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); in bnx2x_sp_rtnl_task()
10217 bnx2x_nic_load(bp, LOAD_NORMAL); in bnx2x_sp_rtnl_task()
10225 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10226 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); in bnx2x_sp_rtnl_task()
10227 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10228 bnx2x_after_function_update(bp); in bnx2x_sp_rtnl_task()
10234 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10236 netif_device_detach(bp->dev); in bnx2x_sp_rtnl_task()
10237 bnx2x_close(bp->dev); in bnx2x_sp_rtnl_task()
10242 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10245 bnx2x_vfpf_set_mcast(bp->dev); in bnx2x_sp_rtnl_task()
10248 &bp->sp_rtnl_state)){ in bnx2x_sp_rtnl_task()
10249 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { in bnx2x_sp_rtnl_task()
10250 bnx2x_tx_disable(bp); in bnx2x_sp_rtnl_task()
10255 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10257 bnx2x_set_rx_mode_inner(bp); in bnx2x_sp_rtnl_task()
10261 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10262 bnx2x_pf_set_vfs_vlan(bp); in bnx2x_sp_rtnl_task()
10264 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10265 bnx2x_dcbx_stop_hw_tx(bp); in bnx2x_sp_rtnl_task()
10266 bnx2x_dcbx_resume_hw_tx(bp); in bnx2x_sp_rtnl_task()
10270 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10271 bnx2x_update_mng_version(bp); in bnx2x_sp_rtnl_task()
10274 port = bp->vxlan_dst_port; in bnx2x_sp_rtnl_task()
10276 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10277 if (!bnx2x_vxlan_port_update(bp, port)) in bnx2x_sp_rtnl_task()
10278 netdev_info(bp->dev, "Added vxlan dest port %d", port); in bnx2x_sp_rtnl_task()
10280 bp->vxlan_dst_port = 0; in bnx2x_sp_rtnl_task()
10284 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10285 if (!bnx2x_vxlan_port_update(bp, 0)) { in bnx2x_sp_rtnl_task()
10286 netdev_info(bp->dev, in bnx2x_sp_rtnl_task()
10288 bp->vxlan_dst_port = 0; in bnx2x_sp_rtnl_task()
10289 vxlan_get_rx_port(bp->dev); in bnx2x_sp_rtnl_task()
10300 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, in bnx2x_sp_rtnl_task()
10301 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10302 bnx2x_disable_sriov(bp); in bnx2x_sp_rtnl_task()
10303 bnx2x_enable_sriov(bp); in bnx2x_sp_rtnl_task()
10309 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); in bnx2x_period_task() local
10311 if (!netif_running(bp->dev)) in bnx2x_period_task()
10314 if (CHIP_REV_IS_SLOW(bp)) { in bnx2x_period_task()
10319 bnx2x_acquire_phy_lock(bp); in bnx2x_period_task()
10326 if (bp->port.pmf) { in bnx2x_period_task()
10327 bnx2x_period_func(&bp->link_params, &bp->link_vars); in bnx2x_period_task()
10330 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); in bnx2x_period_task()
10333 bnx2x_release_phy_lock(bp); in bnx2x_period_task()
10342 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) in bnx2x_get_pretend_reg() argument
10346 return base + (BP_ABS_FUNC(bp)) * stride; in bnx2x_get_pretend_reg()
10349 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, in bnx2x_prev_unload_close_umac() argument
10362 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); in bnx2x_prev_unload_close_umac()
10363 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10368 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, in bnx2x_prev_unload_close_mac() argument
10373 u8 port = BP_PORT(bp); in bnx2x_prev_unload_close_mac()
10378 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_prev_unload_close_mac()
10380 if (!CHIP_IS_E3(bp)) { in bnx2x_prev_unload_close_mac()
10381 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); in bnx2x_prev_unload_close_mac()
10386 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM in bnx2x_prev_unload_close_mac()
10388 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL in bnx2x_prev_unload_close_mac()
10397 wb_data[0] = REG_RD(bp, base_addr + offset); in bnx2x_prev_unload_close_mac()
10398 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); in bnx2x_prev_unload_close_mac()
10403 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10404 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10407 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; in bnx2x_prev_unload_close_mac()
10408 vals->emac_val = REG_RD(bp, vals->emac_addr); in bnx2x_prev_unload_close_mac()
10409 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10414 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_prev_unload_close_mac()
10415 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); in bnx2x_prev_unload_close_mac()
10416 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10418 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10421 vals->xmac_val = REG_RD(bp, vals->xmac_addr); in bnx2x_prev_unload_close_mac()
10422 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10426 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, in bnx2x_prev_unload_close_mac()
10428 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, in bnx2x_prev_unload_close_mac()
10447 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) in bnx2x_prev_is_after_undi() argument
10452 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & in bnx2x_prev_is_after_undi()
10456 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { in bnx2x_prev_is_after_undi()
10464 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) in bnx2x_prev_unload_undi_inc() argument
10469 if (BP_FUNC(bp) < 2) in bnx2x_prev_unload_undi_inc()
10470 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); in bnx2x_prev_unload_undi_inc()
10472 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); in bnx2x_prev_unload_undi_inc()
10474 tmp_reg = REG_RD(bp, addr); in bnx2x_prev_unload_undi_inc()
10479 REG_WR(bp, addr, tmp_reg); in bnx2x_prev_unload_undi_inc()
10482 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); in bnx2x_prev_unload_undi_inc()
10485 static int bnx2x_prev_mcp_done(struct bnx2x *bp) in bnx2x_prev_mcp_done() argument
10487 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, in bnx2x_prev_mcp_done()
10498 bnx2x_prev_path_get_entry(struct bnx2x *bp) in bnx2x_prev_path_get_entry() argument
10503 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && in bnx2x_prev_path_get_entry()
10504 bp->pdev->bus->number == tmp_list->bus && in bnx2x_prev_path_get_entry()
10505 BP_PATH(bp) == tmp_list->path) in bnx2x_prev_path_get_entry()
10511 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) in bnx2x_prev_path_mark_eeh() argument
10522 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_path_mark_eeh()
10528 BP_PATH(bp)); in bnx2x_prev_path_mark_eeh()
10536 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) in bnx2x_prev_is_path_marked() argument
10544 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_is_path_marked()
10548 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10552 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10561 bool bnx2x_port_after_undi(struct bnx2x *bp) in bnx2x_port_after_undi() argument
10568 entry = bnx2x_prev_path_get_entry(bp); in bnx2x_port_after_undi()
10569 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); in bnx2x_port_after_undi()
10576 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) in bnx2x_prev_mark_path() argument
10588 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_mark_path()
10594 BP_PATH(bp)); in bnx2x_prev_mark_path()
10609 tmp_list->bus = bp->pdev->bus->number; in bnx2x_prev_mark_path()
10610 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); in bnx2x_prev_mark_path()
10611 tmp_list->path = BP_PATH(bp); in bnx2x_prev_mark_path()
10613 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; in bnx2x_prev_mark_path()
10621 BP_PATH(bp)); in bnx2x_prev_mark_path()
10629 static int bnx2x_do_flr(struct bnx2x *bp) in bnx2x_do_flr() argument
10631 struct pci_dev *dev = bp->pdev; in bnx2x_do_flr()
10633 if (CHIP_IS_E1x(bp)) { in bnx2x_do_flr()
10639 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { in bnx2x_do_flr()
10641 bp->common.bc_ver); in bnx2x_do_flr()
10649 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); in bnx2x_do_flr()
10654 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) in bnx2x_prev_unload_uncommon() argument
10661 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_uncommon()
10662 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10667 if (bnx2x_prev_is_after_undi(bp)) in bnx2x_prev_unload_uncommon()
10674 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); in bnx2x_prev_unload_uncommon()
10679 rc = bnx2x_do_flr(bp); in bnx2x_prev_unload_uncommon()
10692 rc = bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10699 static int bnx2x_prev_unload_common(struct bnx2x *bp) in bnx2x_prev_unload_common() argument
10713 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_common()
10714 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10716 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); in bnx2x_prev_unload_common()
10723 bnx2x_prev_unload_close_mac(bp, &mac_vals); in bnx2x_prev_unload_common()
10726 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10727 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10728 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10729 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10732 if (bnx2x_prev_is_after_undi(bp)) { in bnx2x_prev_unload_common()
10735 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10737 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); in bnx2x_prev_unload_common()
10739 if (!CHIP_IS_E1x(bp)) in bnx2x_prev_unload_common()
10741 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10744 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10748 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10762 bnx2x_prev_unload_undi_inc(bp, 1); in bnx2x_prev_unload_common()
10772 bnx2x_reset_common(bp); in bnx2x_prev_unload_common()
10775 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); in bnx2x_prev_unload_common()
10777 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10779 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); in bnx2x_prev_unload_common()
10781 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); in bnx2x_prev_unload_common()
10783 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10784 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bnx2x_prev_unload_common()
10787 rc = bnx2x_prev_mark_path(bp, prev_undi); in bnx2x_prev_unload_common()
10789 bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10793 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10796 static int bnx2x_prev_unload(struct bnx2x *bp) in bnx2x_prev_unload() argument
10805 bnx2x_clean_pglue_errors(bp); in bnx2x_prev_unload()
10808 hw_lock_reg = (BP_FUNC(bp) <= 5) ? in bnx2x_prev_unload()
10809 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : in bnx2x_prev_unload()
10810 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); in bnx2x_prev_unload()
10812 hw_lock_val = REG_RD(bp, hw_lock_reg); in bnx2x_prev_unload()
10816 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_prev_unload()
10817 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); in bnx2x_prev_unload()
10821 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
10825 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { in bnx2x_prev_unload()
10827 bnx2x_release_alr(bp); in bnx2x_prev_unload()
10833 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); in bnx2x_prev_unload()
10846 aer = !!(bnx2x_prev_path_get_entry(bp) && in bnx2x_prev_unload()
10847 bnx2x_prev_path_get_entry(bp)->aer); in bnx2x_prev_unload()
10852 rc = bnx2x_prev_unload_common(bp); in bnx2x_prev_unload()
10857 rc = bnx2x_prev_unload_uncommon(bp); in bnx2x_prev_unload()
10870 if (bnx2x_port_after_undi(bp)) in bnx2x_prev_unload()
10871 bp->link_params.feature_config_flags |= in bnx2x_prev_unload()
10879 static void bnx2x_get_common_hwinfo(struct bnx2x *bp) in bnx2x_get_common_hwinfo() argument
10886 val = REG_RD(bp, MISC_REG_CHIP_NUM); in bnx2x_get_common_hwinfo()
10888 val = REG_RD(bp, MISC_REG_CHIP_REV); in bnx2x_get_common_hwinfo()
10894 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); in bnx2x_get_common_hwinfo()
10896 val = REG_RD(bp, MISC_REG_BOND_ID); in bnx2x_get_common_hwinfo()
10898 bp->common.chip_id = id; in bnx2x_get_common_hwinfo()
10901 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { in bnx2x_get_common_hwinfo()
10902 if (CHIP_IS_57810(bp)) in bnx2x_get_common_hwinfo()
10903 bp->common.chip_id = (CHIP_NUM_57811 << 16) | in bnx2x_get_common_hwinfo()
10904 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10905 else if (CHIP_IS_57810_MF(bp)) in bnx2x_get_common_hwinfo()
10906 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | in bnx2x_get_common_hwinfo()
10907 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10908 bp->common.chip_id |= 0x1; in bnx2x_get_common_hwinfo()
10912 bp->db_size = (1 << BNX2X_DB_SHIFT); in bnx2x_get_common_hwinfo()
10914 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_common_hwinfo()
10915 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_get_common_hwinfo()
10917 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_get_common_hwinfo()
10922 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : in bnx2x_get_common_hwinfo()
10925 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_get_common_hwinfo()
10926 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ in bnx2x_get_common_hwinfo()
10928 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ in bnx2x_get_common_hwinfo()
10930 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ in bnx2x_get_common_hwinfo()
10931 bp->pfid = bp->pf_num; /* 0..7 */ in bnx2x_get_common_hwinfo()
10934 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); in bnx2x_get_common_hwinfo()
10936 bp->link_params.chip_id = bp->common.chip_id; in bnx2x_get_common_hwinfo()
10939 val = (REG_RD(bp, 0x2874) & 0x55); in bnx2x_get_common_hwinfo()
10940 if ((bp->common.chip_id & 0x1) || in bnx2x_get_common_hwinfo()
10941 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { in bnx2x_get_common_hwinfo()
10942 bp->flags |= ONE_PORT_FLAG; in bnx2x_get_common_hwinfo()
10946 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); in bnx2x_get_common_hwinfo()
10947 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << in bnx2x_get_common_hwinfo()
10950 bp->common.flash_size, bp->common.flash_size); in bnx2x_get_common_hwinfo()
10952 bnx2x_init_shmem(bp); in bnx2x_get_common_hwinfo()
10954 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? in bnx2x_get_common_hwinfo()
10958 bp->link_params.shmem_base = bp->common.shmem_base; in bnx2x_get_common_hwinfo()
10959 bp->link_params.shmem2_base = bp->common.shmem2_base; in bnx2x_get_common_hwinfo()
10960 if (SHMEM2_RD(bp, size) > in bnx2x_get_common_hwinfo()
10961 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x_get_common_hwinfo()
10962 bp->link_params.lfa_base = in bnx2x_get_common_hwinfo()
10963 REG_RD(bp, bp->common.shmem2_base + in bnx2x_get_common_hwinfo()
10965 lfa_host_addr[BP_PORT(bp)])); in bnx2x_get_common_hwinfo()
10967 bp->link_params.lfa_base = 0; in bnx2x_get_common_hwinfo()
10969 bp->common.shmem_base, bp->common.shmem2_base); in bnx2x_get_common_hwinfo()
10971 if (!bp->common.shmem_base) { in bnx2x_get_common_hwinfo()
10973 bp->flags |= NO_MCP_FLAG; in bnx2x_get_common_hwinfo()
10977 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); in bnx2x_get_common_hwinfo()
10978 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); in bnx2x_get_common_hwinfo()
10980 bp->link_params.hw_led_mode = ((bp->common.hw_config & in bnx2x_get_common_hwinfo()
10984 bp->link_params.feature_config_flags = 0; in bnx2x_get_common_hwinfo()
10985 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); in bnx2x_get_common_hwinfo()
10987 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10990 bp->link_params.feature_config_flags &= in bnx2x_get_common_hwinfo()
10993 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; in bnx2x_get_common_hwinfo()
10994 bp->common.bc_ver = val; in bnx2x_get_common_hwinfo()
11002 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11006 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11009 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11012 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11016 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11020 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? in bnx2x_get_common_hwinfo()
11023 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? in bnx2x_get_common_hwinfo()
11026 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? in bnx2x_get_common_hwinfo()
11029 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? in bnx2x_get_common_hwinfo()
11032 boot_mode = SHMEM_RD(bp, in bnx2x_get_common_hwinfo()
11033 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & in bnx2x_get_common_hwinfo()
11037 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; in bnx2x_get_common_hwinfo()
11040 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; in bnx2x_get_common_hwinfo()
11043 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; in bnx2x_get_common_hwinfo()
11046 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; in bnx2x_get_common_hwinfo()
11050 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); in bnx2x_get_common_hwinfo()
11051 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; in bnx2x_get_common_hwinfo()
11054 (bp->flags & NO_WOL_FLAG) ? "not " : ""); in bnx2x_get_common_hwinfo()
11056 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); in bnx2x_get_common_hwinfo()
11057 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); in bnx2x_get_common_hwinfo()
11058 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); in bnx2x_get_common_hwinfo()
11059 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); in bnx2x_get_common_hwinfo()
11061 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", in bnx2x_get_common_hwinfo()
11068 static int bnx2x_get_igu_cam_info(struct bnx2x *bp) in bnx2x_get_igu_cam_info() argument
11070 int pfid = BP_FUNC(bp); in bnx2x_get_igu_cam_info()
11075 bp->igu_base_sb = 0xff; in bnx2x_get_igu_cam_info()
11076 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_get_igu_cam_info()
11077 int vn = BP_VN(bp); in bnx2x_get_igu_cam_info()
11078 igu_sb_cnt = bp->igu_sb_cnt; in bnx2x_get_igu_cam_info()
11079 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * in bnx2x_get_igu_cam_info()
11082 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + in bnx2x_get_igu_cam_info()
11083 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); in bnx2x_get_igu_cam_info()
11091 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); in bnx2x_get_igu_cam_info()
11100 bp->igu_dsb_id = igu_sb_id; in bnx2x_get_igu_cam_info()
11102 if (bp->igu_base_sb == 0xff) in bnx2x_get_igu_cam_info()
11103 bp->igu_base_sb = igu_sb_id; in bnx2x_get_igu_cam_info()
11116 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); in bnx2x_get_igu_cam_info()
11127 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) in bnx2x_link_settings_supported() argument
11129 int cfg_size = 0, idx, port = BP_PORT(bp); in bnx2x_link_settings_supported()
11132 bp->port.supported[0] = 0; in bnx2x_link_settings_supported()
11133 bp->port.supported[1] = 0; in bnx2x_link_settings_supported()
11134 switch (bp->link_params.num_phys) { in bnx2x_link_settings_supported()
11136 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; in bnx2x_link_settings_supported()
11140 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11144 if (bp->link_params.multi_phy_config & in bnx2x_link_settings_supported()
11146 bp->port.supported[1] = in bnx2x_link_settings_supported()
11147 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11148 bp->port.supported[0] = in bnx2x_link_settings_supported()
11149 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11151 bp->port.supported[0] = in bnx2x_link_settings_supported()
11152 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11153 bp->port.supported[1] = in bnx2x_link_settings_supported()
11154 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11160 if (!(bp->port.supported[0] || bp->port.supported[1])) { in bnx2x_link_settings_supported()
11162 SHMEM_RD(bp, in bnx2x_link_settings_supported()
11164 SHMEM_RD(bp, in bnx2x_link_settings_supported()
11169 if (CHIP_IS_E3(bp)) in bnx2x_link_settings_supported()
11170 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); in bnx2x_link_settings_supported()
11174 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11175 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bnx2x_link_settings_supported()
11178 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11179 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bnx2x_link_settings_supported()
11183 bp->port.link_config[0]); in bnx2x_link_settings_supported()
11187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); in bnx2x_link_settings_supported()
11190 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11192 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; in bnx2x_link_settings_supported()
11194 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11196 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; in bnx2x_link_settings_supported()
11198 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11200 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; in bnx2x_link_settings_supported()
11202 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11204 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; in bnx2x_link_settings_supported()
11206 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11208 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | in bnx2x_link_settings_supported()
11211 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11213 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; in bnx2x_link_settings_supported()
11215 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11217 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; in bnx2x_link_settings_supported()
11219 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11221 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; in bnx2x_link_settings_supported()
11224 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], in bnx2x_link_settings_supported()
11225 bp->port.supported[1]); in bnx2x_link_settings_supported()
11228 static void bnx2x_link_settings_requested(struct bnx2x *bp) in bnx2x_link_settings_requested() argument
11231 bp->port.advertising[0] = 0; in bnx2x_link_settings_requested()
11232 bp->port.advertising[1] = 0; in bnx2x_link_settings_requested()
11233 switch (bp->link_params.num_phys) { in bnx2x_link_settings_requested()
11243 bp->link_params.req_duplex[idx] = DUPLEX_FULL; in bnx2x_link_settings_requested()
11244 link_config = bp->port.link_config[idx]; in bnx2x_link_settings_requested()
11247 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { in bnx2x_link_settings_requested()
11248 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11250 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11251 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11252 if (bp->link_params.phy[EXT_PHY1].type == in bnx2x_link_settings_requested()
11254 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11259 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11261 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11269 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { in bnx2x_link_settings_requested()
11270 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11272 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11278 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11284 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { in bnx2x_link_settings_requested()
11285 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11287 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11289 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11295 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11301 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11303 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11305 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11311 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11317 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11319 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11321 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11323 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11329 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11335 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11337 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11339 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11342 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11344 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11346 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11351 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11357 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11359 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11361 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11367 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11373 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11375 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11377 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11380 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11382 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11384 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11390 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11395 bp->link_params.req_line_speed[idx] = SPEED_20000; in bnx2x_link_settings_requested()
11401 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11403 bp->port.advertising[idx] = in bnx2x_link_settings_requested()
11404 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11408 bp->link_params.req_flow_ctrl[idx] = (link_config & in bnx2x_link_settings_requested()
11410 if (bp->link_params.req_flow_ctrl[idx] == in bnx2x_link_settings_requested()
11412 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) in bnx2x_link_settings_requested()
11413 bp->link_params.req_flow_ctrl[idx] = in bnx2x_link_settings_requested()
11416 bnx2x_set_requested_fc(bp); in bnx2x_link_settings_requested()
11420 bp->link_params.req_line_speed[idx], in bnx2x_link_settings_requested()
11421 bp->link_params.req_duplex[idx], in bnx2x_link_settings_requested()
11422 bp->link_params.req_flow_ctrl[idx], in bnx2x_link_settings_requested()
11423 bp->port.advertising[idx]); in bnx2x_link_settings_requested()
11435 static void bnx2x_get_port_hwinfo(struct bnx2x *bp) in bnx2x_get_port_hwinfo() argument
11437 int port = BP_PORT(bp); in bnx2x_get_port_hwinfo()
11441 bp->link_params.bp = bp; in bnx2x_get_port_hwinfo()
11442 bp->link_params.port = port; in bnx2x_get_port_hwinfo()
11444 bp->link_params.lane_config = in bnx2x_get_port_hwinfo()
11445 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); in bnx2x_get_port_hwinfo()
11447 bp->link_params.speed_cap_mask[0] = in bnx2x_get_port_hwinfo()
11448 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11451 bp->link_params.speed_cap_mask[1] = in bnx2x_get_port_hwinfo()
11452 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11455 bp->port.link_config[0] = in bnx2x_get_port_hwinfo()
11456 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); in bnx2x_get_port_hwinfo()
11458 bp->port.link_config[1] = in bnx2x_get_port_hwinfo()
11459 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); in bnx2x_get_port_hwinfo()
11461 bp->link_params.multi_phy_config = in bnx2x_get_port_hwinfo()
11462 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); in bnx2x_get_port_hwinfo()
11466 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); in bnx2x_get_port_hwinfo()
11467 bp->wol = (!(bp->flags & NO_WOL_FLAG) && in bnx2x_get_port_hwinfo()
11471 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) in bnx2x_get_port_hwinfo()
11472 bp->flags |= NO_ISCSI_FLAG; in bnx2x_get_port_hwinfo()
11474 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) in bnx2x_get_port_hwinfo()
11475 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_port_hwinfo()
11478 bp->link_params.lane_config, in bnx2x_get_port_hwinfo()
11479 bp->link_params.speed_cap_mask[0], in bnx2x_get_port_hwinfo()
11480 bp->port.link_config[0]); in bnx2x_get_port_hwinfo()
11482 bp->link_params.switch_cfg = (bp->port.link_config[0] & in bnx2x_get_port_hwinfo()
11484 bnx2x_phy_probe(&bp->link_params); in bnx2x_get_port_hwinfo()
11485 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); in bnx2x_get_port_hwinfo()
11487 bnx2x_link_settings_requested(bp); in bnx2x_get_port_hwinfo()
11494 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11498 bp->mdio.prtad = bp->port.phy_addr; in bnx2x_get_port_hwinfo()
11502 bp->mdio.prtad = in bnx2x_get_port_hwinfo()
11506 eee_mode = (((SHMEM_RD(bp, dev_info. in bnx2x_get_port_hwinfo()
11511 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | in bnx2x_get_port_hwinfo()
11515 bp->link_params.eee_mode = 0; in bnx2x_get_port_hwinfo()
11519 void bnx2x_get_iscsi_info(struct bnx2x *bp) in bnx2x_get_iscsi_info() argument
11522 int port = BP_PORT(bp); in bnx2x_get_iscsi_info()
11523 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_iscsi_info()
11526 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_iscsi_info()
11527 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11532 bp->cnic_eth_dev.max_iscsi_conn = in bnx2x_get_iscsi_info()
11537 bp->cnic_eth_dev.max_iscsi_conn); in bnx2x_get_iscsi_info()
11543 if (!bp->cnic_eth_dev.max_iscsi_conn) in bnx2x_get_iscsi_info()
11544 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11547 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) in bnx2x_get_ext_wwn_info() argument
11550 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_ext_wwn_info()
11551 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); in bnx2x_get_ext_wwn_info()
11552 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_ext_wwn_info()
11553 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); in bnx2x_get_ext_wwn_info()
11556 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_ext_wwn_info()
11557 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); in bnx2x_get_ext_wwn_info()
11558 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_ext_wwn_info()
11559 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); in bnx2x_get_ext_wwn_info()
11562 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) in bnx2x_shared_fcoe_funcs() argument
11566 if (IS_MF(bp)) { in bnx2x_shared_fcoe_funcs()
11570 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { in bnx2x_shared_fcoe_funcs()
11571 if (IS_MF_SD(bp)) { in bnx2x_shared_fcoe_funcs()
11572 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11580 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11590 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; in bnx2x_shared_fcoe_funcs()
11593 u32 lic = SHMEM_RD(bp, in bnx2x_shared_fcoe_funcs()
11604 static void bnx2x_get_fcoe_info(struct bnx2x *bp) in bnx2x_get_fcoe_info() argument
11606 int port = BP_PORT(bp); in bnx2x_get_fcoe_info()
11607 int func = BP_ABS_FUNC(bp); in bnx2x_get_fcoe_info()
11608 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11610 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); in bnx2x_get_fcoe_info()
11612 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_fcoe_info()
11613 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11618 bp->cnic_eth_dev.max_fcoe_conn = in bnx2x_get_fcoe_info()
11623 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; in bnx2x_get_fcoe_info()
11627 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; in bnx2x_get_fcoe_info()
11630 if (!IS_MF(bp)) { in bnx2x_get_fcoe_info()
11632 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_fcoe_info()
11633 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11636 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_fcoe_info()
11637 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11642 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_fcoe_info()
11643 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11646 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_fcoe_info()
11647 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11650 } else if (!IS_MF_SD(bp)) { in bnx2x_get_fcoe_info()
11654 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) in bnx2x_get_fcoe_info()
11655 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11657 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) in bnx2x_get_fcoe_info()
11658 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11661 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); in bnx2x_get_fcoe_info()
11667 if (!bp->cnic_eth_dev.max_fcoe_conn) in bnx2x_get_fcoe_info()
11668 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11671 static void bnx2x_get_cnic_info(struct bnx2x *bp) in bnx2x_get_cnic_info() argument
11678 bnx2x_get_iscsi_info(bp); in bnx2x_get_cnic_info()
11679 bnx2x_get_fcoe_info(bp); in bnx2x_get_cnic_info()
11682 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_cnic_mac_hwinfo() argument
11685 int func = BP_ABS_FUNC(bp); in bnx2x_get_cnic_mac_hwinfo()
11686 int port = BP_PORT(bp); in bnx2x_get_cnic_mac_hwinfo()
11687 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; in bnx2x_get_cnic_mac_hwinfo()
11688 u8 *fip_mac = bp->fip_mac; in bnx2x_get_cnic_mac_hwinfo()
11690 if (IS_MF(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11696 if (!IS_MF_SD(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11697 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); in bnx2x_get_cnic_mac_hwinfo()
11699 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11701 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11707 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11711 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11713 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11719 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11722 bp->mf_ext_config = cfg; in bnx2x_get_cnic_mac_hwinfo()
11725 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11727 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11732 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11734 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11745 if (IS_MF_FCOE_AFEX(bp)) in bnx2x_get_cnic_mac_hwinfo()
11746 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11748 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11750 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11754 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11756 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11763 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11769 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11770 eth_zero_addr(bp->fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11774 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_mac_hwinfo() argument
11777 int func = BP_ABS_FUNC(bp); in bnx2x_get_mac_hwinfo()
11778 int port = BP_PORT(bp); in bnx2x_get_mac_hwinfo()
11781 eth_zero_addr(bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11783 if (BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11785 eth_hw_addr_random(bp->dev); in bnx2x_get_mac_hwinfo()
11786 } else if (IS_MF(bp)) { in bnx2x_get_mac_hwinfo()
11787 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in bnx2x_get_mac_hwinfo()
11788 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); in bnx2x_get_mac_hwinfo()
11791 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); in bnx2x_get_mac_hwinfo()
11793 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11794 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11797 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11798 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11799 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); in bnx2x_get_mac_hwinfo()
11801 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11802 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11805 if (!BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11807 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11808 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11809 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); in bnx2x_get_mac_hwinfo()
11810 bp->flags |= HAS_PHYS_PORT_ID; in bnx2x_get_mac_hwinfo()
11813 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_mac_hwinfo()
11815 if (!is_valid_ether_addr(bp->dev->dev_addr)) in bnx2x_get_mac_hwinfo()
11816 dev_err(&bp->pdev->dev, in bnx2x_get_mac_hwinfo()
11819 bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11822 static bool bnx2x_get_dropless_info(struct bnx2x *bp) in bnx2x_get_dropless_info() argument
11827 if (IS_VF(bp)) in bnx2x_get_dropless_info()
11830 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { in bnx2x_get_dropless_info()
11832 tmp = BP_ABS_FUNC(bp); in bnx2x_get_dropless_info()
11833 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); in bnx2x_get_dropless_info()
11837 tmp = BP_PORT(bp); in bnx2x_get_dropless_info()
11838 cfg = SHMEM_RD(bp, in bnx2x_get_dropless_info()
11845 static void validate_set_si_mode(struct bnx2x *bp) in validate_set_si_mode() argument
11847 u8 func = BP_ABS_FUNC(bp); in validate_set_si_mode()
11850 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in validate_set_si_mode()
11854 bp->mf_mode = MULTI_FUNCTION_SI; in validate_set_si_mode()
11855 bp->mf_config[BP_VN(bp)] = in validate_set_si_mode()
11856 MF_CFG_RD(bp, func_mf_config[func].config); in validate_set_si_mode()
11861 static int bnx2x_get_hwinfo(struct bnx2x *bp) in bnx2x_get_hwinfo() argument
11863 int /*abs*/func = BP_ABS_FUNC(bp); in bnx2x_get_hwinfo()
11869 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { in bnx2x_get_hwinfo()
11870 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11875 bnx2x_get_common_hwinfo(bp); in bnx2x_get_hwinfo()
11880 if (CHIP_IS_E1x(bp)) { in bnx2x_get_hwinfo()
11881 bp->common.int_block = INT_BLOCK_HC; in bnx2x_get_hwinfo()
11883 bp->igu_dsb_id = DEF_SB_IGU_ID; in bnx2x_get_hwinfo()
11884 bp->igu_base_sb = 0; in bnx2x_get_hwinfo()
11886 bp->common.int_block = INT_BLOCK_IGU; in bnx2x_get_hwinfo()
11889 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11891 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_get_hwinfo()
11899 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); in bnx2x_get_hwinfo()
11900 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
11902 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11907 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11908 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11910 bnx2x_release_hw_lock(bp, in bnx2x_get_hwinfo()
11918 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; in bnx2x_get_hwinfo()
11922 rc = bnx2x_get_igu_cam_info(bp); in bnx2x_get_hwinfo()
11923 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11933 if (CHIP_IS_E1x(bp)) in bnx2x_get_hwinfo()
11934 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); in bnx2x_get_hwinfo()
11940 bp->base_fw_ndsb = bp->igu_base_sb; in bnx2x_get_hwinfo()
11943 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, in bnx2x_get_hwinfo()
11944 bp->igu_sb_cnt, bp->base_fw_ndsb); in bnx2x_get_hwinfo()
11950 bp->mf_ov = 0; in bnx2x_get_hwinfo()
11951 bp->mf_mode = 0; in bnx2x_get_hwinfo()
11952 bp->mf_sub_mode = 0; in bnx2x_get_hwinfo()
11953 vn = BP_VN(bp); in bnx2x_get_hwinfo()
11954 mfw_vn = BP_FW_MB_IDX(bp); in bnx2x_get_hwinfo()
11956 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { in bnx2x_get_hwinfo()
11958 bp->common.shmem2_base, SHMEM2_RD(bp, size), in bnx2x_get_hwinfo()
11961 if (SHMEM2_HAS(bp, mf_cfg_addr)) in bnx2x_get_hwinfo()
11962 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); in bnx2x_get_hwinfo()
11964 bp->common.mf_cfg_base = bp->common.shmem_base + in bnx2x_get_hwinfo()
11975 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
11977 val = SHMEM_RD(bp, in bnx2x_get_hwinfo()
11983 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
11986 if ((!CHIP_IS_E1x(bp)) && in bnx2x_get_hwinfo()
11987 (MF_CFG_RD(bp, func_mf_config[func]. in bnx2x_get_hwinfo()
11989 (SHMEM2_HAS(bp, in bnx2x_get_hwinfo()
11991 bp->mf_mode = MULTI_FUNCTION_AFEX; in bnx2x_get_hwinfo()
11992 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12000 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12005 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12006 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12012 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12013 bp->mf_sub_mode = SUB_MF_MODE_BD; in bnx2x_get_hwinfo()
12014 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12015 MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12018 if (SHMEM2_HAS(bp, mtu_size)) { in bnx2x_get_hwinfo()
12019 int mtu_idx = BP_FW_MB_IDX(bp); in bnx2x_get_hwinfo()
12023 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); in bnx2x_get_hwinfo()
12033 bp->dev->mtu = mtu_size; in bnx2x_get_hwinfo()
12037 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12038 bp->mf_sub_mode = SUB_MF_MODE_UFP; in bnx2x_get_hwinfo()
12039 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12040 MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12044 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12047 val2 = SHMEM_RD(bp, in bnx2x_get_hwinfo()
12052 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
12053 bp->mf_sub_mode = in bnx2x_get_hwinfo()
12058 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12065 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12071 IS_MF(bp) ? "multi" : "single"); in bnx2x_get_hwinfo()
12073 switch (bp->mf_mode) { in bnx2x_get_hwinfo()
12075 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_get_hwinfo()
12078 bp->mf_ov = val; in bnx2x_get_hwinfo()
12079 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12082 func, bp->mf_ov, bp->mf_ov); in bnx2x_get_hwinfo()
12083 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || in bnx2x_get_hwinfo()
12084 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { in bnx2x_get_hwinfo()
12085 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12088 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12090 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12105 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12118 if (CHIP_MODE_IS_4_PORT(bp) && in bnx2x_get_hwinfo()
12119 !bp->path_has_ovlan && in bnx2x_get_hwinfo()
12120 !IS_MF(bp) && in bnx2x_get_hwinfo()
12121 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
12122 u8 other_port = !BP_PORT(bp); in bnx2x_get_hwinfo()
12123 u8 other_func = BP_PATH(bp) + 2*other_port; in bnx2x_get_hwinfo()
12124 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12127 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12132 if (CHIP_IS_E1H(bp) && IS_MF(bp)) in bnx2x_get_hwinfo()
12133 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); in bnx2x_get_hwinfo()
12136 bnx2x_get_port_hwinfo(bp); in bnx2x_get_hwinfo()
12139 bnx2x_get_mac_hwinfo(bp); in bnx2x_get_hwinfo()
12141 bnx2x_get_cnic_info(bp); in bnx2x_get_hwinfo()
12146 static void bnx2x_read_fwinfo(struct bnx2x *bp) in bnx2x_read_fwinfo() argument
12156 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); in bnx2x_read_fwinfo()
12157 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); in bnx2x_read_fwinfo()
12182 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, in bnx2x_read_fwinfo()
12219 memcpy(bp->fw_ver, &vpd_data[rodi], len); in bnx2x_read_fwinfo()
12220 bp->fw_ver[len] = ' '; in bnx2x_read_fwinfo()
12231 static void bnx2x_set_modes_bitmap(struct bnx2x *bp) in bnx2x_set_modes_bitmap() argument
12235 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_set_modes_bitmap()
12237 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_set_modes_bitmap()
12242 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_set_modes_bitmap()
12247 if (CHIP_IS_E2(bp)) in bnx2x_set_modes_bitmap()
12249 else if (CHIP_IS_E3(bp)) { in bnx2x_set_modes_bitmap()
12251 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_set_modes_bitmap()
12257 if (IS_MF(bp)) { in bnx2x_set_modes_bitmap()
12259 switch (bp->mf_mode) { in bnx2x_set_modes_bitmap()
12278 INIT_MODE_FLAGS(bp) = flags; in bnx2x_set_modes_bitmap()
12281 static int bnx2x_init_bp(struct bnx2x *bp) in bnx2x_init_bp() argument
12286 mutex_init(&bp->port.phy_mutex); in bnx2x_init_bp()
12287 mutex_init(&bp->fw_mb_mutex); in bnx2x_init_bp()
12288 mutex_init(&bp->drv_info_mutex); in bnx2x_init_bp()
12289 sema_init(&bp->stats_lock, 1); in bnx2x_init_bp()
12290 bp->drv_info_mng_owner = false; in bnx2x_init_bp()
12291 INIT_LIST_HEAD(&bp->vlan_reg); in bnx2x_init_bp()
12293 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); in bnx2x_init_bp()
12294 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); in bnx2x_init_bp()
12295 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); in bnx2x_init_bp()
12296 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); in bnx2x_init_bp()
12297 if (IS_PF(bp)) { in bnx2x_init_bp()
12298 rc = bnx2x_get_hwinfo(bp); in bnx2x_init_bp()
12302 eth_zero_addr(bp->dev->dev_addr); in bnx2x_init_bp()
12305 bnx2x_set_modes_bitmap(bp); in bnx2x_init_bp()
12307 rc = bnx2x_alloc_mem_bp(bp); in bnx2x_init_bp()
12311 bnx2x_read_fwinfo(bp); in bnx2x_init_bp()
12313 func = BP_FUNC(bp); in bnx2x_init_bp()
12316 if (IS_PF(bp) && !BP_NOMCP(bp)) { in bnx2x_init_bp()
12318 bp->fw_seq = in bnx2x_init_bp()
12319 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_init_bp()
12321 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); in bnx2x_init_bp()
12323 rc = bnx2x_prev_unload(bp); in bnx2x_init_bp()
12325 bnx2x_free_mem_bp(bp); in bnx2x_init_bp()
12330 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_init_bp()
12331 dev_err(&bp->pdev->dev, "FPGA detected\n"); in bnx2x_init_bp()
12333 if (BP_NOMCP(bp) && (func == 0)) in bnx2x_init_bp()
12334 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); in bnx2x_init_bp()
12336 bp->disable_tpa = disable_tpa; in bnx2x_init_bp()
12337 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); in bnx2x_init_bp()
12339 bp->disable_tpa |= is_kdump_kernel(); in bnx2x_init_bp()
12342 if (bp->disable_tpa) { in bnx2x_init_bp()
12343 bp->dev->hw_features &= ~NETIF_F_LRO; in bnx2x_init_bp()
12344 bp->dev->features &= ~NETIF_F_LRO; in bnx2x_init_bp()
12347 if (CHIP_IS_E1(bp)) in bnx2x_init_bp()
12348 bp->dropless_fc = 0; in bnx2x_init_bp()
12350 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); in bnx2x_init_bp()
12352 bp->mrrs = mrrs; in bnx2x_init_bp()
12354 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; in bnx2x_init_bp()
12355 if (IS_VF(bp)) in bnx2x_init_bp()
12356 bp->rx_ring_size = MAX_RX_AVAIL; in bnx2x_init_bp()
12359 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12360 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12362 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; in bnx2x_init_bp()
12364 init_timer(&bp->timer); in bnx2x_init_bp()
12365 bp->timer.expires = jiffies + bp->current_interval; in bnx2x_init_bp()
12366 bp->timer.data = (unsigned long) bp; in bnx2x_init_bp()
12367 bp->timer.function = bnx2x_timer; in bnx2x_init_bp()
12369 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12370 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && in bnx2x_init_bp()
12371 SHMEM2_RD(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12372 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { in bnx2x_init_bp()
12373 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); in bnx2x_init_bp()
12374 bnx2x_dcbx_init_params(bp); in bnx2x_init_bp()
12376 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); in bnx2x_init_bp()
12379 if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12380 bp->cnic_base_cl_id = FP_SB_MAX_E1x; in bnx2x_init_bp()
12382 bp->cnic_base_cl_id = FP_SB_MAX_E2; in bnx2x_init_bp()
12385 if (IS_VF(bp)) in bnx2x_init_bp()
12386 bp->max_cos = 1; in bnx2x_init_bp()
12387 else if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12388 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; in bnx2x_init_bp()
12389 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) in bnx2x_init_bp()
12390 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; in bnx2x_init_bp()
12391 else if (CHIP_IS_E3B0(bp)) in bnx2x_init_bp()
12392 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; in bnx2x_init_bp()
12395 CHIP_NUM(bp), CHIP_REV(bp)); in bnx2x_init_bp()
12396 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); in bnx2x_init_bp()
12402 if (IS_VF(bp)) in bnx2x_init_bp()
12403 bp->min_msix_vec_cnt = 1; in bnx2x_init_bp()
12404 else if (CNIC_SUPPORT(bp)) in bnx2x_init_bp()
12405 bp->min_msix_vec_cnt = 3; in bnx2x_init_bp()
12407 bp->min_msix_vec_cnt = 2; in bnx2x_init_bp()
12408 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); in bnx2x_init_bp()
12410 bp->dump_preset_idx = 1; in bnx2x_init_bp()
12412 if (CHIP_IS_E3B0(bp)) in bnx2x_init_bp()
12413 bp->flags |= PTP_SUPPORTED; in bnx2x_init_bp()
12429 struct bnx2x *bp = netdev_priv(dev); in bnx2x_open() local
12432 bp->stats_init = true; in bnx2x_open()
12436 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_open()
12444 if (IS_PF(bp)) { in bnx2x_open()
12445 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_open()
12449 other_load_status = bnx2x_get_load_status(bp, other_engine); in bnx2x_open()
12450 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_open()
12451 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || in bnx2x_open()
12452 bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_open()
12460 bnx2x_set_reset_global(bp); in bnx2x_open()
12469 bnx2x_trylock_leader_lock(bp) && in bnx2x_open()
12470 !bnx2x_leader_reset(bp)) { in bnx2x_open()
12471 netdev_info(bp->dev, in bnx2x_open()
12477 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_open()
12478 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_open()
12488 bp->recovery_state = BNX2X_RECOVERY_DONE; in bnx2x_open()
12489 rc = bnx2x_nic_load(bp, LOAD_OPEN); in bnx2x_open()
12494 if (IS_PF(bp)) in bnx2x_open()
12504 struct bnx2x *bp = netdev_priv(dev); in bnx2x_close() local
12507 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); in bnx2x_close()
12512 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, in bnx2x_init_mcast_macs_list() argument
12515 int mc_count = netdev_mc_count(bp->dev); in bnx2x_init_mcast_macs_list()
12525 netdev_for_each_mc_addr(ha, bp->dev) { in bnx2x_init_mcast_macs_list()
12554 static int bnx2x_set_uc_list(struct bnx2x *bp) in bnx2x_set_uc_list() argument
12557 struct net_device *dev = bp->dev; in bnx2x_set_uc_list()
12559 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; in bnx2x_set_uc_list()
12563 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); in bnx2x_set_uc_list()
12570 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, in bnx2x_set_uc_list()
12588 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, in bnx2x_set_uc_list()
12592 static int bnx2x_set_mc_list(struct bnx2x *bp) in bnx2x_set_mc_list() argument
12594 struct net_device *dev = bp->dev; in bnx2x_set_mc_list()
12598 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list()
12601 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_set_mc_list()
12609 rc = bnx2x_init_mcast_macs_list(bp, &rparam); in bnx2x_set_mc_list()
12617 rc = bnx2x_config_mcast(bp, &rparam, in bnx2x_set_mc_list()
12632 struct bnx2x *bp = netdev_priv(dev); in bnx2x_set_rx_mode() local
12634 if (bp->state != BNX2X_STATE_OPEN) { in bnx2x_set_rx_mode()
12635 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); in bnx2x_set_rx_mode()
12639 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, in bnx2x_set_rx_mode()
12644 void bnx2x_set_rx_mode_inner(struct bnx2x *bp) in bnx2x_set_rx_mode_inner() argument
12648 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); in bnx2x_set_rx_mode_inner()
12650 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12652 if (bp->dev->flags & IFF_PROMISC) { in bnx2x_set_rx_mode_inner()
12654 } else if ((bp->dev->flags & IFF_ALLMULTI) || in bnx2x_set_rx_mode_inner()
12655 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && in bnx2x_set_rx_mode_inner()
12656 CHIP_IS_E1(bp))) { in bnx2x_set_rx_mode_inner()
12659 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12661 if (bnx2x_set_mc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12665 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12666 if (bnx2x_set_uc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12668 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12673 bnx2x_schedule_sp_rtnl(bp, in bnx2x_set_rx_mode_inner()
12678 bp->rx_mode = rx_mode; in bnx2x_set_rx_mode_inner()
12680 if (IS_MF_ISCSI_ONLY(bp)) in bnx2x_set_rx_mode_inner()
12681 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_set_rx_mode_inner()
12684 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { in bnx2x_set_rx_mode_inner()
12685 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_set_rx_mode_inner()
12686 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12690 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12691 bnx2x_set_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12692 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12698 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12699 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12707 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_read() local
12717 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_read()
12718 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); in bnx2x_mdio_read()
12719 bnx2x_release_phy_lock(bp); in bnx2x_mdio_read()
12731 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_write() local
12741 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_write()
12742 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); in bnx2x_mdio_write()
12743 bnx2x_release_phy_lock(bp); in bnx2x_mdio_write()
12750 struct bnx2x *bp = netdev_priv(dev); in bnx2x_ioctl() local
12758 return bnx2x_hwtstamp_ioctl(bp, ifr); in bnx2x_ioctl()
12762 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); in bnx2x_ioctl()
12769 struct bnx2x *bp = netdev_priv(dev); in poll_bnx2x() local
12772 for_each_eth_queue(bp, i) { in poll_bnx2x()
12773 struct bnx2x_fastpath *fp = &bp->fp[i]; in poll_bnx2x()
12774 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); in poll_bnx2x()
12781 struct bnx2x *bp = netdev_priv(dev); in bnx2x_validate_addr() local
12784 if (IS_VF(bp)) in bnx2x_validate_addr()
12785 bnx2x_sample_bulletin(bp); in bnx2x_validate_addr()
12797 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_get_phys_port_id() local
12799 if (!(bp->flags & HAS_PHYS_PORT_ID)) in bnx2x_get_phys_port_id()
12802 ppid->id_len = sizeof(bp->phys_port_id); in bnx2x_get_phys_port_id()
12803 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); in bnx2x_get_phys_port_id()
12816 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) in __bnx2x_vlan_configure_vid() argument
12820 if (IS_PF(bp)) { in __bnx2x_vlan_configure_vid()
12824 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, in __bnx2x_vlan_configure_vid()
12827 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); in __bnx2x_vlan_configure_vid()
12833 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) in bnx2x_vlan_reconfigure_vid() argument
12838 if (!bp->vlan_cnt) { in bnx2x_vlan_reconfigure_vid()
12843 list_for_each_entry(vlan, &bp->vlan_reg, link) { in bnx2x_vlan_reconfigure_vid()
12855 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); in bnx2x_vlan_reconfigure_vid()
12869 struct bnx2x *bp = netdev_priv(dev); in bnx2x_vlan_rx_add_vid() local
12874 if (!netif_running(bp->dev)) { in bnx2x_vlan_rx_add_vid()
12886 bp->vlan_cnt++; in bnx2x_vlan_rx_add_vid()
12887 if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) { in bnx2x_vlan_rx_add_vid()
12889 bp->accept_any_vlan = true; in bnx2x_vlan_rx_add_vid()
12890 if (IS_PF(bp)) in bnx2x_vlan_rx_add_vid()
12891 bnx2x_set_rx_mode_inner(bp); in bnx2x_vlan_rx_add_vid()
12893 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_vlan_rx_add_vid()
12894 } else if (bp->vlan_cnt <= bp->vlan_credit) { in bnx2x_vlan_rx_add_vid()
12895 rc = __bnx2x_vlan_configure_vid(bp, vid, true); in bnx2x_vlan_rx_add_vid()
12903 list_add(&vlan->link, &bp->vlan_reg); in bnx2x_vlan_rx_add_vid()
12905 bp->vlan_cnt--; in bnx2x_vlan_rx_add_vid()
12916 struct bnx2x *bp = netdev_priv(dev); in bnx2x_vlan_rx_kill_vid() local
12920 if (!netif_running(bp->dev)) { in bnx2x_vlan_rx_kill_vid()
12928 if (!bp->vlan_cnt) { in bnx2x_vlan_rx_kill_vid()
12933 list_for_each_entry(vlan, &bp->vlan_reg, link) in bnx2x_vlan_rx_kill_vid()
12943 rc = __bnx2x_vlan_configure_vid(bp, vid, false); in bnx2x_vlan_rx_kill_vid()
12948 bp->vlan_cnt--; in bnx2x_vlan_rx_kill_vid()
12950 if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) { in bnx2x_vlan_rx_kill_vid()
12952 list_for_each_entry(vlan, &bp->vlan_reg, link) { in bnx2x_vlan_rx_kill_vid()
12956 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); in bnx2x_vlan_rx_kill_vid()
12967 bp->accept_any_vlan = false; in bnx2x_vlan_rx_kill_vid()
12968 if (IS_PF(bp)) in bnx2x_vlan_rx_kill_vid()
12969 bnx2x_set_rx_mode_inner(bp); in bnx2x_vlan_rx_kill_vid()
12971 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_vlan_rx_kill_vid()
13019 static int bnx2x_set_coherency_mask(struct bnx2x *bp) in bnx2x_set_coherency_mask() argument
13021 struct device *dev = &bp->pdev->dev; in bnx2x_set_coherency_mask()
13032 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) in bnx2x_disable_pcie_error_reporting() argument
13034 if (bp->flags & AER_ENABLED) { in bnx2x_disable_pcie_error_reporting()
13035 pci_disable_pcie_error_reporting(bp->pdev); in bnx2x_disable_pcie_error_reporting()
13036 bp->flags &= ~AER_ENABLED; in bnx2x_disable_pcie_error_reporting()
13040 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, in bnx2x_init_dev() argument
13051 bp->dev = dev; in bnx2x_init_dev()
13052 bp->pdev = pdev; in bnx2x_init_dev()
13056 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13062 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13068 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { in bnx2x_init_dev()
13069 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); in bnx2x_init_dev()
13085 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13094 if (IS_PF(bp)) { in bnx2x_init_dev()
13096 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13104 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); in bnx2x_init_dev()
13109 rc = bnx2x_set_coherency_mask(bp); in bnx2x_init_dev()
13119 bp->regview = pci_ioremap_bar(pdev, 0); in bnx2x_init_dev()
13120 if (!bp->regview) { in bnx2x_init_dev()
13121 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13133 bp->pf_num = PCI_FUNC(pdev->devfn); in bnx2x_init_dev()
13136 pci_read_config_dword(bp->pdev, in bnx2x_init_dev()
13138 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> in bnx2x_init_dev()
13141 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); in bnx2x_init_dev()
13144 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_init_dev()
13153 bp->flags |= AER_ENABLED; in bnx2x_init_dev()
13161 if (IS_PF(bp)) { in bnx2x_init_dev()
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
13163 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
13164 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
13165 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
13168 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
13169 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
13170 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
13171 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
13179 REG_WR(bp, in bnx2x_init_dev()
13186 bnx2x_set_ethtool_ops(bp, dev); in bnx2x_init_dev()
13209 if (IS_PF(bp)) { in bnx2x_init_dev()
13211 bp->accept_any_vlan = true; in bnx2x_init_dev()
13215 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { in bnx2x_init_dev()
13231 bp->mdio.prtad = MDIO_PRTAD_NONE; in bnx2x_init_dev()
13232 bp->mdio.mmds = 0; in bnx2x_init_dev()
13233 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; in bnx2x_init_dev()
13234 bp->mdio.dev = dev; in bnx2x_init_dev()
13235 bp->mdio.mdio_read = bnx2x_mdio_read; in bnx2x_init_dev()
13236 bp->mdio.mdio_write = bnx2x_mdio_write; in bnx2x_init_dev()
13251 static int bnx2x_check_firmware(struct bnx2x *bp) in bnx2x_check_firmware() argument
13253 const struct firmware *firmware = bp->firmware; in bnx2x_check_firmware()
13375 bp->arr = kmalloc(len, GFP_KERNEL); \
13376 if (!bp->arr) \
13378 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13379 (u8 *)bp->arr, len); \
13382 static int bnx2x_init_firmware(struct bnx2x *bp) in bnx2x_init_firmware() argument
13388 if (bp->firmware) in bnx2x_init_firmware()
13391 if (CHIP_IS_E1(bp)) in bnx2x_init_firmware()
13393 else if (CHIP_IS_E1H(bp)) in bnx2x_init_firmware()
13395 else if (!CHIP_IS_E1x(bp)) in bnx2x_init_firmware()
13403 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); in bnx2x_init_firmware()
13410 rc = bnx2x_check_firmware(bp); in bnx2x_init_firmware()
13416 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; in bnx2x_init_firmware()
13430 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13432 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13434 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13436 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13438 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13440 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13442 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13444 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13452 kfree(bp->init_ops_offsets); in bnx2x_init_firmware()
13454 kfree(bp->init_ops); in bnx2x_init_firmware()
13456 kfree(bp->init_data); in bnx2x_init_firmware()
13458 release_firmware(bp->firmware); in bnx2x_init_firmware()
13459 bp->firmware = NULL; in bnx2x_init_firmware()
13464 static void bnx2x_release_firmware(struct bnx2x *bp) in bnx2x_release_firmware() argument
13466 kfree(bp->init_ops_offsets); in bnx2x_release_firmware()
13467 kfree(bp->init_ops); in bnx2x_release_firmware()
13468 kfree(bp->init_data); in bnx2x_release_firmware()
13469 release_firmware(bp->firmware); in bnx2x_release_firmware()
13470 bp->firmware = NULL; in bnx2x_release_firmware()
13490 void bnx2x__init_func_obj(struct bnx2x *bp) in bnx2x__init_func_obj() argument
13493 bnx2x_setup_dmae(bp); in bnx2x__init_func_obj()
13495 bnx2x_init_func_obj(bp, &bp->func_obj, in bnx2x__init_func_obj()
13496 bnx2x_sp(bp, func_rdata), in bnx2x__init_func_obj()
13497 bnx2x_sp_mapping(bp, func_rdata), in bnx2x__init_func_obj()
13498 bnx2x_sp(bp, func_afex_rdata), in bnx2x__init_func_obj()
13499 bnx2x_sp_mapping(bp, func_afex_rdata), in bnx2x__init_func_obj()
13504 static int bnx2x_set_qm_cid_count(struct bnx2x *bp) in bnx2x_set_qm_cid_count() argument
13506 int cid_count = BNX2X_L2_MAX_CID(bp); in bnx2x_set_qm_cid_count()
13508 if (IS_SRIOV(bp)) in bnx2x_set_qm_cid_count()
13511 if (CNIC_SUPPORT(bp)) in bnx2x_set_qm_cid_count()
13611 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, in bnx2x_send_update_drift_ramrod() argument
13622 func_params.f_obj = &bp->func_obj; in bnx2x_send_update_drift_ramrod()
13633 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_update_drift_ramrod()
13638 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjfreq() local
13646 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjfreq()
13691 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, in bnx2x_ptp_adjfreq()
13706 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjtime() local
13710 timecounter_adjtime(&bp->timecounter, delta); in bnx2x_ptp_adjtime()
13717 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_gettime() local
13720 ns = timecounter_read(&bp->timecounter); in bnx2x_ptp_gettime()
13732 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_settime() local
13740 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); in bnx2x_ptp_settime()
13749 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_enable() local
13755 static void bnx2x_register_phc(struct bnx2x *bp) in bnx2x_register_phc() argument
13758 bp->ptp_clock_info.owner = THIS_MODULE; in bnx2x_register_phc()
13759 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); in bnx2x_register_phc()
13760 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ in bnx2x_register_phc()
13761 bp->ptp_clock_info.n_alarm = 0; in bnx2x_register_phc()
13762 bp->ptp_clock_info.n_ext_ts = 0; in bnx2x_register_phc()
13763 bp->ptp_clock_info.n_per_out = 0; in bnx2x_register_phc()
13764 bp->ptp_clock_info.pps = 0; in bnx2x_register_phc()
13765 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; in bnx2x_register_phc()
13766 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; in bnx2x_register_phc()
13767 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; in bnx2x_register_phc()
13768 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; in bnx2x_register_phc()
13769 bp->ptp_clock_info.enable = bnx2x_ptp_enable; in bnx2x_register_phc()
13771 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); in bnx2x_register_phc()
13772 if (IS_ERR(bp->ptp_clock)) { in bnx2x_register_phc()
13773 bp->ptp_clock = NULL; in bnx2x_register_phc()
13782 struct bnx2x *bp; in bnx2x_init_one() local
13836 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); in bnx2x_init_one()
13840 bp = netdev_priv(dev); in bnx2x_init_one()
13842 bp->flags = 0; in bnx2x_init_one()
13844 bp->flags |= IS_VF_FLAG; in bnx2x_init_one()
13846 bp->igu_sb_cnt = max_non_def_sbs; in bnx2x_init_one()
13847 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; in bnx2x_init_one()
13848 bp->msg_enable = debug; in bnx2x_init_one()
13849 bp->cnic_support = cnic_cnt; in bnx2x_init_one()
13850 bp->cnic_probe = bnx2x_cnic_probe; in bnx2x_init_one()
13854 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); in bnx2x_init_one()
13861 IS_PF(bp) ? "physical" : "virtual"); in bnx2x_init_one()
13862 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); in bnx2x_init_one()
13867 rc = bnx2x_init_bp(bp); in bnx2x_init_one()
13875 if (IS_VF(bp)) { in bnx2x_init_one()
13876 bp->doorbells = bnx2x_vf_doorbells(bp); in bnx2x_init_one()
13877 rc = bnx2x_vf_pci_alloc(bp); in bnx2x_init_one()
13881 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); in bnx2x_init_one()
13883 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13888 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), in bnx2x_init_one()
13891 if (!bp->doorbells) { in bnx2x_init_one()
13892 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13898 if (IS_VF(bp)) { in bnx2x_init_one()
13899 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); in bnx2x_init_one()
13905 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); in bnx2x_init_one()
13910 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); in bnx2x_init_one()
13911 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); in bnx2x_init_one()
13914 if (CHIP_IS_E1x(bp)) in bnx2x_init_one()
13915 bp->flags |= NO_FCOE_FLAG; in bnx2x_init_one()
13918 bnx2x_set_num_queues(bp); in bnx2x_init_one()
13923 rc = bnx2x_set_int_mode(bp); in bnx2x_init_one()
13938 if (!NO_FCOE(bp)) { in bnx2x_init_one()
13941 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in bnx2x_init_one()
13944 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || in bnx2x_init_one()
13952 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), in bnx2x_init_one()
13958 dev->base_addr, bp->pdev->irq, dev->dev_addr); in bnx2x_init_one()
13960 bnx2x_register_phc(bp); in bnx2x_init_one()
13962 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) in bnx2x_init_one()
13963 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); in bnx2x_init_one()
13968 bnx2x_disable_pcie_error_reporting(bp); in bnx2x_init_one()
13970 if (bp->regview) in bnx2x_init_one()
13971 iounmap(bp->regview); in bnx2x_init_one()
13973 if (IS_PF(bp) && bp->doorbells) in bnx2x_init_one()
13974 iounmap(bp->doorbells); in bnx2x_init_one()
13988 struct bnx2x *bp, in __bnx2x_remove() argument
13991 if (bp->ptp_clock) { in __bnx2x_remove()
13992 ptp_clock_unregister(bp->ptp_clock); in __bnx2x_remove()
13993 bp->ptp_clock = NULL; in __bnx2x_remove()
13997 if (!NO_FCOE(bp)) { in __bnx2x_remove()
13999 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in __bnx2x_remove()
14005 bnx2x_dcbnl_update_applist(bp, true); in __bnx2x_remove()
14008 if (IS_PF(bp) && in __bnx2x_remove()
14009 !BP_NOMCP(bp) && in __bnx2x_remove()
14010 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) in __bnx2x_remove()
14011 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); in __bnx2x_remove()
14022 bnx2x_iov_remove_one(bp); in __bnx2x_remove()
14025 if (IS_PF(bp)) { in __bnx2x_remove()
14026 bnx2x_set_power_state(bp, PCI_D0); in __bnx2x_remove()
14027 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); in __bnx2x_remove()
14032 bnx2x_reset_endianity(bp); in __bnx2x_remove()
14036 bnx2x_disable_msi(bp); in __bnx2x_remove()
14039 if (IS_PF(bp)) in __bnx2x_remove()
14040 bnx2x_set_power_state(bp, PCI_D3hot); in __bnx2x_remove()
14043 cancel_delayed_work_sync(&bp->sp_rtnl_task); in __bnx2x_remove()
14046 if (IS_VF(bp)) in __bnx2x_remove()
14047 bnx2x_vfpf_release(bp); in __bnx2x_remove()
14051 pci_wake_from_d3(pdev, bp->wol); in __bnx2x_remove()
14055 bnx2x_disable_pcie_error_reporting(bp); in __bnx2x_remove()
14057 if (bp->regview) in __bnx2x_remove()
14058 iounmap(bp->regview); in __bnx2x_remove()
14063 if (IS_PF(bp)) { in __bnx2x_remove()
14064 if (bp->doorbells) in __bnx2x_remove()
14065 iounmap(bp->doorbells); in __bnx2x_remove()
14067 bnx2x_release_firmware(bp); in __bnx2x_remove()
14069 bnx2x_vf_pci_dealloc(bp); in __bnx2x_remove()
14071 bnx2x_free_mem_bp(bp); in __bnx2x_remove()
14085 struct bnx2x *bp; in bnx2x_remove_one() local
14091 bp = netdev_priv(dev); in bnx2x_remove_one()
14093 __bnx2x_remove(pdev, dev, bp, true); in bnx2x_remove_one()
14096 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) in bnx2x_eeh_nic_unload() argument
14098 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; in bnx2x_eeh_nic_unload()
14100 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_eeh_nic_unload()
14102 if (CNIC_LOADED(bp)) in bnx2x_eeh_nic_unload()
14103 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); in bnx2x_eeh_nic_unload()
14106 bnx2x_tx_disable(bp); in bnx2x_eeh_nic_unload()
14108 bnx2x_del_all_napi(bp); in bnx2x_eeh_nic_unload()
14109 if (CNIC_LOADED(bp)) in bnx2x_eeh_nic_unload()
14110 bnx2x_del_all_napi_cnic(bp); in bnx2x_eeh_nic_unload()
14111 netdev_reset_tc(bp->dev); in bnx2x_eeh_nic_unload()
14113 del_timer_sync(&bp->timer); in bnx2x_eeh_nic_unload()
14114 cancel_delayed_work_sync(&bp->sp_task); in bnx2x_eeh_nic_unload()
14115 cancel_delayed_work_sync(&bp->period_task); in bnx2x_eeh_nic_unload()
14117 if (!down_timeout(&bp->stats_lock, HZ / 10)) { in bnx2x_eeh_nic_unload()
14118 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_eeh_nic_unload()
14119 up(&bp->stats_lock); in bnx2x_eeh_nic_unload()
14122 bnx2x_save_statistics(bp); in bnx2x_eeh_nic_unload()
14124 netif_carrier_off(bp->dev); in bnx2x_eeh_nic_unload()
14141 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_error_detected() local
14155 bnx2x_eeh_nic_unload(bp); in bnx2x_io_error_detected()
14157 bnx2x_prev_path_mark_eeh(bp); in bnx2x_io_error_detected()
14176 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_slot_reset() local
14193 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_io_slot_reset()
14199 bnx2x_init_shmem(bp); in bnx2x_io_slot_reset()
14201 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { in bnx2x_io_slot_reset()
14204 v = SHMEM2_RD(bp, in bnx2x_io_slot_reset()
14205 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); in bnx2x_io_slot_reset()
14206 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], in bnx2x_io_slot_reset()
14209 bnx2x_drain_tx_queues(bp); in bnx2x_io_slot_reset()
14210 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); in bnx2x_io_slot_reset()
14211 bnx2x_netif_stop(bp, 1); in bnx2x_io_slot_reset()
14212 bnx2x_free_irq(bp); in bnx2x_io_slot_reset()
14215 bnx2x_send_unload_done(bp, true); in bnx2x_io_slot_reset()
14217 bp->sp_state = 0; in bnx2x_io_slot_reset()
14218 bp->port.pmf = 0; in bnx2x_io_slot_reset()
14220 bnx2x_prev_unload(bp); in bnx2x_io_slot_reset()
14225 bnx2x_squeeze_objects(bp); in bnx2x_io_slot_reset()
14226 bnx2x_free_skbs(bp); in bnx2x_io_slot_reset()
14227 for_each_rx_queue(bp, i) in bnx2x_io_slot_reset()
14228 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); in bnx2x_io_slot_reset()
14229 bnx2x_free_fp_mem(bp); in bnx2x_io_slot_reset()
14230 bnx2x_free_mem(bp); in bnx2x_io_slot_reset()
14232 bp->state = BNX2X_STATE_CLOSED; in bnx2x_io_slot_reset()
14238 if (bp->flags & AER_ENABLED) { in bnx2x_io_slot_reset()
14258 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_resume() local
14260 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { in bnx2x_io_resume()
14261 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); in bnx2x_io_resume()
14267 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_io_resume()
14271 bnx2x_nic_load(bp, LOAD_NORMAL); in bnx2x_io_resume()
14287 struct bnx2x *bp; in bnx2x_shutdown() local
14292 bp = netdev_priv(dev); in bnx2x_shutdown()
14293 if (!bp) in bnx2x_shutdown()
14304 __bnx2x_remove(pdev, dev, bp, false); in bnx2x_shutdown()
14366 void bnx2x_notify_link_changed(struct bnx2x *bp) in bnx2x_notify_link_changed() argument
14368 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); in bnx2x_notify_link_changed()
14383 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) in bnx2x_set_iscsi_eth_mac_addr() argument
14388 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, in bnx2x_set_iscsi_eth_mac_addr()
14389 &bp->iscsi_l2_mac_obj, true, in bnx2x_set_iscsi_eth_mac_addr()
14394 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) in bnx2x_cnic_sp_post() argument
14400 if (unlikely(bp->panic)) in bnx2x_cnic_sp_post()
14404 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14405 BUG_ON(bp->cnic_spq_pending < count); in bnx2x_cnic_sp_post()
14406 bp->cnic_spq_pending -= count; in bnx2x_cnic_sp_post()
14408 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { in bnx2x_cnic_sp_post()
14409 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) in bnx2x_cnic_sp_post()
14412 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) in bnx2x_cnic_sp_post()
14420 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / in bnx2x_cnic_sp_post()
14422 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - in bnx2x_cnic_sp_post()
14424 bnx2x_set_ctx_validation(bp, in bnx2x_cnic_sp_post()
14425 &bp->context[cxt_index]. in bnx2x_cnic_sp_post()
14427 BNX2X_ISCSI_ETH_CID(bp)); in bnx2x_cnic_sp_post()
14438 if (!atomic_read(&bp->cq_spq_left)) in bnx2x_cnic_sp_post()
14441 atomic_dec(&bp->cq_spq_left); in bnx2x_cnic_sp_post()
14443 if (!atomic_read(&bp->eq_spq_left)) in bnx2x_cnic_sp_post()
14446 atomic_dec(&bp->eq_spq_left); in bnx2x_cnic_sp_post()
14449 if (bp->cnic_spq_pending >= in bnx2x_cnic_sp_post()
14450 bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_post()
14453 bp->cnic_spq_pending++; in bnx2x_cnic_sp_post()
14460 spe = bnx2x_sp_get_next(bp); in bnx2x_cnic_sp_post()
14461 *spe = *bp->cnic_kwq_cons; in bnx2x_cnic_sp_post()
14464 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); in bnx2x_cnic_sp_post()
14466 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) in bnx2x_cnic_sp_post()
14467 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_cnic_sp_post()
14469 bp->cnic_kwq_cons++; in bnx2x_cnic_sp_post()
14471 bnx2x_sp_prod_update(bp); in bnx2x_cnic_sp_post()
14472 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14478 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_sp_queue() local
14482 if (unlikely(bp->panic)) { in bnx2x_cnic_sp_queue()
14488 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && in bnx2x_cnic_sp_queue()
14489 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_cnic_sp_queue()
14494 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14499 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) in bnx2x_cnic_sp_queue()
14502 *bp->cnic_kwq_prod = *spe; in bnx2x_cnic_sp_queue()
14504 bp->cnic_kwq_pending++; in bnx2x_cnic_sp_queue()
14510 bp->cnic_kwq_pending); in bnx2x_cnic_sp_queue()
14512 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) in bnx2x_cnic_sp_queue()
14513 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_cnic_sp_queue()
14515 bp->cnic_kwq_prod++; in bnx2x_cnic_sp_queue()
14518 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14520 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_queue()
14521 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_sp_queue()
14526 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send() argument
14531 mutex_lock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14532 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2x_cnic_ctl_send()
14533 lockdep_is_held(&bp->cnic_mutex)); in bnx2x_cnic_ctl_send()
14535 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send()
14536 mutex_unlock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14541 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send_bh() argument
14547 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_cnic_ctl_send_bh()
14549 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send_bh()
14558 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) in bnx2x_cnic_notify() argument
14564 return bnx2x_cnic_ctl_send(bp, &ctl); in bnx2x_cnic_notify()
14567 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) in bnx2x_cnic_cfc_comp() argument
14576 bnx2x_cnic_ctl_send_bh(bp, &ctl); in bnx2x_cnic_cfc_comp()
14577 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_cfc_comp()
14585 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) in bnx2x_set_iscsi_eth_rx_mode() argument
14588 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_set_iscsi_eth_rx_mode()
14604 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14609 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14611 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_set_iscsi_eth_rx_mode()
14612 set_bit(sched_state, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14615 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, in bnx2x_set_iscsi_eth_rx_mode()
14622 struct bnx2x *bp = netdev_priv(dev); in bnx2x_drv_ctl() local
14630 bnx2x_ilt_wr(bp, index, addr); in bnx2x_drv_ctl()
14637 bnx2x_cnic_sp_post(bp, count); in bnx2x_drv_ctl()
14643 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_drv_ctl()
14647 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14649 cp->iscsi_l2_cid, BP_FUNC(bp), in bnx2x_drv_ctl()
14650 bnx2x_sp(bp, mac_rdata), in bnx2x_drv_ctl()
14651 bnx2x_sp_mapping(bp, mac_rdata), in bnx2x_drv_ctl()
14653 &bp->sp_state, BNX2X_OBJ_TYPE_RX, in bnx2x_drv_ctl()
14654 &bp->macs_pool); in bnx2x_drv_ctl()
14657 rc = bnx2x_set_iscsi_eth_mac_addr(bp); in bnx2x_drv_ctl()
14667 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_drv_ctl()
14674 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14686 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_drv_ctl()
14693 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14700 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14708 atomic_add(count, &bp->cq_spq_left); in bnx2x_drv_ctl()
14715 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14716 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14717 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14718 int path = BP_PATH(bp); in bnx2x_drv_ctl()
14719 int port = BP_PORT(bp); in bnx2x_drv_ctl()
14729 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14732 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || in bnx2x_drv_ctl()
14733 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) in bnx2x_drv_ctl()
14737 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); in bnx2x_drv_ctl()
14746 REG_WR(bp, scratch_offset + i, in bnx2x_drv_ctl()
14749 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14756 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14757 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14760 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14765 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14767 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14777 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { in bnx2x_drv_ctl()
14782 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14786 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14790 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14804 struct bnx2x *bp = netdev_priv(dev); in bnx2x_get_fc_npiv() local
14810 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) in bnx2x_get_fc_npiv()
14821 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); in bnx2x_get_fc_npiv()
14825 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { in bnx2x_get_fc_npiv()
14863 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) in bnx2x_setup_cnic_irq_info() argument
14865 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_irq_info()
14867 if (bp->flags & USING_MSIX_FLAG) { in bnx2x_setup_cnic_irq_info()
14870 cp->irq_arr[0].vector = bp->msix_table[1].vector; in bnx2x_setup_cnic_irq_info()
14875 if (!CHIP_IS_E1x(bp)) in bnx2x_setup_cnic_irq_info()
14876 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; in bnx2x_setup_cnic_irq_info()
14878 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; in bnx2x_setup_cnic_irq_info()
14880 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14881 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14882 cp->irq_arr[1].status_blk = bp->def_status_blk; in bnx2x_setup_cnic_irq_info()
14889 void bnx2x_setup_cnic_info(struct bnx2x *bp) in bnx2x_setup_cnic_info() argument
14891 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_info()
14893 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_setup_cnic_info()
14894 bnx2x_cid_ilt_lines(bp); in bnx2x_setup_cnic_info()
14895 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_setup_cnic_info()
14896 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_setup_cnic_info()
14897 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_setup_cnic_info()
14900 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, in bnx2x_setup_cnic_info()
14903 if (NO_ISCSI_OOO(bp)) in bnx2x_setup_cnic_info()
14910 struct bnx2x *bp = netdev_priv(dev); in bnx2x_register_cnic() local
14911 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_register_cnic()
14921 if (!CNIC_SUPPORT(bp)) { in bnx2x_register_cnic()
14926 if (!CNIC_LOADED(bp)) { in bnx2x_register_cnic()
14927 rc = bnx2x_load_cnic(bp); in bnx2x_register_cnic()
14934 bp->cnic_enabled = true; in bnx2x_register_cnic()
14936 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); in bnx2x_register_cnic()
14937 if (!bp->cnic_kwq) in bnx2x_register_cnic()
14940 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_register_cnic()
14941 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_register_cnic()
14942 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; in bnx2x_register_cnic()
14944 bp->cnic_spq_pending = 0; in bnx2x_register_cnic()
14945 bp->cnic_kwq_pending = 0; in bnx2x_register_cnic()
14947 bp->cnic_data = data; in bnx2x_register_cnic()
14951 cp->iro_arr = bp->iro_arr; in bnx2x_register_cnic()
14953 bnx2x_setup_cnic_irq_info(bp); in bnx2x_register_cnic()
14955 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2x_register_cnic()
14958 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_register_cnic()
14965 struct bnx2x *bp = netdev_priv(dev); in bnx2x_unregister_cnic() local
14966 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_unregister_cnic()
14968 mutex_lock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
14970 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2x_unregister_cnic()
14971 mutex_unlock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
14973 bp->cnic_enabled = false; in bnx2x_unregister_cnic()
14974 kfree(bp->cnic_kwq); in bnx2x_unregister_cnic()
14975 bp->cnic_kwq = NULL; in bnx2x_unregister_cnic()
14982 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_probe() local
14983 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_cnic_probe()
14989 if (NO_ISCSI(bp) && NO_FCOE(bp)) in bnx2x_cnic_probe()
14993 cp->chip_id = CHIP_ID(bp); in bnx2x_cnic_probe()
14994 cp->pdev = bp->pdev; in bnx2x_cnic_probe()
14995 cp->io_base = bp->regview; in bnx2x_cnic_probe()
14996 cp->io_base2 = bp->doorbells; in bnx2x_cnic_probe()
14999 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_cnic_probe()
15000 bnx2x_cid_ilt_lines(bp); in bnx2x_cnic_probe()
15002 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_cnic_probe()
15008 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_cnic_probe()
15010 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_cnic_probe()
15011 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_cnic_probe()
15013 if (NO_ISCSI_OOO(bp)) in bnx2x_cnic_probe()
15016 if (NO_ISCSI(bp)) in bnx2x_cnic_probe()
15019 if (NO_FCOE(bp)) in bnx2x_cnic_probe()
15033 struct bnx2x *bp = fp->bp; in bnx2x_rx_ustorm_prods_offset() local
15036 if (IS_VF(bp)) in bnx2x_rx_ustorm_prods_offset()
15037 return bnx2x_vf_ustorm_prods_offset(bp, fp); in bnx2x_rx_ustorm_prods_offset()
15038 else if (!CHIP_IS_E1x(bp)) in bnx2x_rx_ustorm_prods_offset()
15041 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); in bnx2x_rx_ustorm_prods_offset()
15051 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) in bnx2x_pretend_func() argument
15055 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) in bnx2x_pretend_func()
15059 pretend_reg = bnx2x_get_pretend_reg(bp); in bnx2x_pretend_func()
15060 REG_WR(bp, pretend_reg, pretend_func_val); in bnx2x_pretend_func()
15061 REG_RD(bp, pretend_reg); in bnx2x_pretend_func()
15067 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); in bnx2x_ptp_task() local
15068 int port = BP_PORT(bp); in bnx2x_ptp_task()
15074 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
15078 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : in bnx2x_ptp_task()
15081 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : in bnx2x_ptp_task()
15084 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
15086 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_ptp_task()
15090 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); in bnx2x_ptp_task()
15091 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_ptp_task()
15092 bp->ptp_tx_skb = NULL; in bnx2x_ptp_task()
15099 schedule_work(&bp->ptp_task); in bnx2x_ptp_task()
15103 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) in bnx2x_set_rx_ts() argument
15105 int port = BP_PORT(bp); in bnx2x_set_rx_ts()
15108 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : in bnx2x_set_rx_ts()
15111 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : in bnx2x_set_rx_ts()
15115 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_set_rx_ts()
15118 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_set_rx_ts()
15129 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); in bnx2x_cyclecounter_read() local
15130 int port = BP_PORT(bp); in bnx2x_cyclecounter_read()
15134 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : in bnx2x_cyclecounter_read()
15144 static void bnx2x_init_cyclecounter(struct bnx2x *bp) in bnx2x_init_cyclecounter() argument
15146 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); in bnx2x_init_cyclecounter()
15147 bp->cyclecounter.read = bnx2x_cyclecounter_read; in bnx2x_init_cyclecounter()
15148 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); in bnx2x_init_cyclecounter()
15149 bp->cyclecounter.shift = 1; in bnx2x_init_cyclecounter()
15150 bp->cyclecounter.mult = 1; in bnx2x_init_cyclecounter()
15153 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) in bnx2x_send_reset_timesync_ramrod() argument
15163 func_params.f_obj = &bp->func_obj; in bnx2x_send_reset_timesync_ramrod()
15170 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_reset_timesync_ramrod()
15173 static int bnx2x_enable_ptp_packets(struct bnx2x *bp) in bnx2x_enable_ptp_packets() argument
15188 for_each_eth_queue(bp, i) { in bnx2x_enable_ptp_packets()
15189 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_enable_ptp_packets()
15192 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_enable_ptp_packets()
15195 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_enable_ptp_packets()
15205 int bnx2x_configure_ptp_filters(struct bnx2x *bp) in bnx2x_configure_ptp_filters() argument
15207 int port = BP_PORT(bp); in bnx2x_configure_ptp_filters()
15210 if (!bp->hwtstamp_ioctl_called) in bnx2x_configure_ptp_filters()
15213 switch (bp->tx_type) { in bnx2x_configure_ptp_filters()
15215 bp->flags |= TX_TIMESTAMPING_EN; in bnx2x_configure_ptp_filters()
15216 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15218 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15226 switch (bp->rx_filter) { in bnx2x_configure_ptp_filters()
15231 bp->rx_filter = HWTSTAMP_FILTER_NONE; in bnx2x_configure_ptp_filters()
15236 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in bnx2x_configure_ptp_filters()
15238 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15240 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15246 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in bnx2x_configure_ptp_filters()
15248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15256 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in bnx2x_configure_ptp_filters()
15258 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15260 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15267 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in bnx2x_configure_ptp_filters()
15269 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15271 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15277 rc = bnx2x_enable_ptp_packets(bp); in bnx2x_configure_ptp_filters()
15282 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp_filters()
15288 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) in bnx2x_hwtstamp_ioctl() argument
15306 bp->hwtstamp_ioctl_called = 1; in bnx2x_hwtstamp_ioctl()
15307 bp->tx_type = config.tx_type; in bnx2x_hwtstamp_ioctl()
15308 bp->rx_filter = config.rx_filter; in bnx2x_hwtstamp_ioctl()
15310 rc = bnx2x_configure_ptp_filters(bp); in bnx2x_hwtstamp_ioctl()
15314 config.rx_filter = bp->rx_filter; in bnx2x_hwtstamp_ioctl()
15321 static int bnx2x_configure_ptp(struct bnx2x *bp) in bnx2x_configure_ptp() argument
15323 int rc, port = BP_PORT(bp); in bnx2x_configure_ptp()
15327 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15329 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15331 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15333 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15337 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp()
15341 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_configure_ptp()
15347 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); in bnx2x_configure_ptp()
15350 rc = bnx2x_send_reset_timesync_ramrod(bp); in bnx2x_configure_ptp()
15357 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_configure_ptp()
15359 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_configure_ptp()
15366 void bnx2x_init_ptp(struct bnx2x *bp) in bnx2x_init_ptp() argument
15371 rc = bnx2x_configure_ptp(bp); in bnx2x_init_ptp()
15378 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); in bnx2x_init_ptp()
15384 if (!bp->timecounter_init_done) { in bnx2x_init_ptp()
15385 bnx2x_init_cyclecounter(bp); in bnx2x_init_ptp()
15386 timecounter_init(&bp->timecounter, &bp->cyclecounter, in bnx2x_init_ptp()
15388 bp->timecounter_init_done = 1; in bnx2x_init_ptp()