351 			val = rd32(&pf->hw,  in i40e_tx_timeout()
355 			val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);  in i40e_tx_timeout()
563 		new_data = rd32(hw, loreg);  in i40e_stat_update48()
564 		new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;  in i40e_stat_update48()
590 	new_data = rd32(hw, reg);  in i40e_stat_update32()
1162 	val = rd32(hw, I40E_PRTPM_EEE_STAT);  in i40e_update_pf_stats()
3147 	rd32(hw, I40E_PFINT_ICR0);         /* read to clear */  in i40e_enable_misc_int_causes()
3420 	icr0 = rd32(hw, I40E_PFINT_ICR0);  in i40e_intr()
3421 	ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_intr()
3445 		u32 qval = rd32(hw, I40E_QINT_RQCTL(0));  in i40e_intr()
3450 		qval = rd32(hw, I40E_QINT_TQCTL(0));  in i40e_intr()
3477 		val = rd32(hw, I40E_GLGEN_RSTAT);  in i40e_intr()
3494 			 rd32(hw, I40E_PFHMC_ERRORINFO),  in i40e_intr()
3495 			 rd32(hw, I40E_PFHMC_ERRORDATA));  in i40e_intr()
3499 		u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);  in i40e_intr()
3782 		tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));  in i40e_pf_txq_wait()
3815 			tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));  in i40e_vsi_control_tx()
3870 		rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));  in i40e_pf_rxq_wait()
3897 			rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));  in i40e_vsi_control_rx()
3993 			val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));  in i40e_vsi_free_irq()
4003 				val = rd32(hw, I40E_QINT_RQCTL(qp));  in i40e_vsi_free_irq()
4015 				val = rd32(hw, I40E_QINT_TQCTL(qp));  in i40e_vsi_free_irq()
4035 		val = rd32(hw, I40E_PFINT_LNKLST0);  in i40e_vsi_free_irq()
4042 		val = rd32(hw, I40E_QINT_RQCTL(qp));  in i40e_vsi_free_irq()
4053 		val = rd32(hw, I40E_QINT_TQCTL(qp));  in i40e_vsi_free_irq()
4357 		val = rd32(&pf->hw,  in i40e_detect_recover_hung_queue()
4361 		val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);  in i40e_detect_recover_hung_queue()
5461 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_do_reset()
5472 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_do_reset()
5756 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);  in i40e_get_cur_guaranteed_fd_count()
5769 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);  in i40e_get_current_fd_count()
5784 	val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);  in i40e_get_global_fd_count()
5888 		reg = rd32(&pf->hw, I40E_PFQF_CTL_1);  in i40e_fdir_flush_and_replay()
6192 	val = rd32(&pf->hw, pf->hw.aq.arq.len);  in i40e_clean_adminq_subtask()
6209 	val = rd32(&pf->hw, pf->hw.aq.asq.len);  in i40e_clean_adminq_subtask()
6283 	val = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_clean_adminq_subtask()
6571 	if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {  in i40e_fdir_sb_setup()
6898 	reg = rd32(hw, I40E_GL_MDET_TX);  in i40e_handle_mdd_event()
6915 	reg = rd32(hw, I40E_GL_MDET_RX);  in i40e_handle_mdd_event()
6932 		reg = rd32(hw, I40E_PF_MDET_TX);  in i40e_handle_mdd_event()
6938 		reg = rd32(hw, I40E_PF_MDET_RX);  in i40e_handle_mdd_event()
6954 		reg = rd32(hw, I40E_VP_MDET_TX(i));  in i40e_handle_mdd_event()
6962 		reg = rd32(hw, I40E_VP_MDET_RX(i));  in i40e_handle_mdd_event()
6981 	reg = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_handle_mdd_event()
7894 	hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |  in i40e_config_rss()
7895 		((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);  in i40e_config_rss()
7904 	reg_val = rd32(hw, I40E_PFQF_CTL_0);  in i40e_config_rss()
10260 	    (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {  in i40e_probe()
10534 		val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);  in i40e_probe()
10832 		reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_pci_error_slot_reset()