275 		wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);  in i40e_config_irq_link_list()
298 	wr32(hw, reg_idx, reg);  in i40e_config_irq_link_list()
335 		wr32(hw, reg_idx, reg);  in i40e_config_irq_link_list()
346 			wr32(hw, I40E_GLINT_CTL, reg);  in i40e_config_irq_link_list()
416 	wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl);  in i40e_config_vsi_tx_queue()
602 	wr32(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),  in i40e_enable_vf_mappings()
607 	wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg);  in i40e_enable_vf_mappings()
614 		wr32(hw, I40E_VPLAN_QTABLE(total_queue_pairs, vf->vf_id), reg);  in i40e_enable_vf_mappings()
630 		wr32(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id), reg);  in i40e_enable_vf_mappings()
649 	wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), 0);  in i40e_disable_vf_mappings()
651 		wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_id),  in i40e_disable_vf_mappings()
686 		wr32(hw, reg_idx, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);  in i40e_free_vf_res()
701 		wr32(hw, reg_idx, reg);  in i40e_free_vf_res()
764 	wr32(hw, I40E_PF_PCI_CIAA,  in i40e_quiesce_vf_pci()
803 		wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);  in i40e_reset_vf()
834 	wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_COMPLETED);  in i40e_reset_vf()
838 	wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);  in i40e_reset_vf()
854 	wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);  in i40e_reset_vf()
921 			wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));  in i40e_free_vfs()
2019 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);  in i40e_vc_process_vflr_event()
2031 			wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));  in i40e_vc_process_vflr_event()