Lines Matching refs:wr32
189 wr32(hw, I40E_VFINT_DYN_CTL01, 0); in i40evf_misc_irq_disable()
205 wr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK | in i40evf_misc_irq_enable()
207 wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); in i40evf_misc_irq_enable()
226 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), 0); in i40evf_irq_disable()
245 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), in i40evf_irq_enable_queues()
269 wr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl); in i40evf_fire_sw_int()
277 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl); in i40evf_fire_sw_int()
317 wr32(hw, I40E_VFINT_DYN_CTL01, val); in i40evf_msix_aq()
1282 wr32(hw, I40E_VFQF_HKEY(i), seed_dw[i]); in i40evf_configure_rss_reg()
1293 wr32(hw, I40E_VFQF_HLUT(i), lut); in i40evf_configure_rss_reg()
1312 wr32(hw, I40E_VFQF_HENA(0), (u32)hena); in i40evf_configure_rss()
1313 wr32(hw, I40E_VFQF_HENA(1), (u32)(hena >> 32)); in i40evf_configure_rss()
1831 wr32(hw, hw->aq.arq.len, val); in i40evf_adminq_task()
1848 wr32(hw, hw->aq.asq.len, val); in i40evf_adminq_task()