968 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)  in mvpp2_read()  function
1042 	pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,  in mvpp2_prs_hw_read()
1048 		pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));  in mvpp2_prs_hw_read()
1053 		pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));  in mvpp2_prs_hw_read()
2125 	val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);  in mvpp2_prs_hw_port_init()
2131 	val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));  in mvpp2_prs_hw_port_init()
2139 	val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));  in mvpp2_prs_hw_port_init()
3322 	val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);  in mvpp2_cls_port_config()
3355 	val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);  in mvpp2_cls_oversize_rxq_set()
3389 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));  in mvpp2_bm_pool_create()
3426 		buf_phys_addr = mvpp2_read(priv,  in mvpp2_bm_bufs_free()
3428 		vaddr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);  in mvpp2_bm_bufs_free()
3455 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));  in mvpp2_bm_pool_destroy()
3523 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_long_pool_set()
3541 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_short_pool_set()
3964 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);  in mvpp2_defaults_set()
3980 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_defaults_set()
3998 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_enable()
4011 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_disable()
4050 	reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &  in mvpp2_egress_disable()
4071 		reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);  in mvpp2_egress_disable()
4081 	u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));  in mvpp2_rxq_received()
4121 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_offset_set()
4151 	val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);  in mvpp2_txq_pend_desc_num_get()
4183 		u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu));  in mvpp2_aggr_desc_num_check()
4203 	val = mvpp2_read(priv, MVPP2_TXQ_RSVD_RSLT_REG);  in mvpp2_txq_alloc_reserved_desc()
4304 	val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));  in mvpp2_txq_sent_desc_proc()
4318 		mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));  in mvpp2_txq_sent_counter_clear()
4340 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);  in mvpp2_txp_max_tx_size_set()
4346 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);  in mvpp2_txp_max_tx_size_set()
4356 		val = mvpp2_read(port->priv,  in mvpp2_txp_max_tx_size_set()
4503 	aggr_txq->next_desc_to_proc = mvpp2_read(priv,  in mvpp2_aggr_txq_init()
4633 	val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);  in mvpp2_txq_init()
4654 	val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));  in mvpp2_txq_init()
4740 	val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);  in mvpp2_txq_clean()
4784 	val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);  in mvpp2_cleanup_txqs()
5380 	cause_rx_tx = mvpp2_read(port->priv,  in mvpp2_poll()