Lines Matching refs:param
1678 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) in mlx4_INIT_HCA() argument
1812 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); in mlx4_INIT_HCA()
1813 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); in mlx4_INIT_HCA()
1814 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); in mlx4_INIT_HCA()
1815 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); in mlx4_INIT_HCA()
1816 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); in mlx4_INIT_HCA()
1817 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); in mlx4_INIT_HCA()
1818 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); in mlx4_INIT_HCA()
1819 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); in mlx4_INIT_HCA()
1820 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); in mlx4_INIT_HCA()
1821 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); in mlx4_INIT_HCA()
1822 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); in mlx4_INIT_HCA()
1823 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); in mlx4_INIT_HCA()
1824 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); in mlx4_INIT_HCA()
1833 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); in mlx4_INIT_HCA()
1834 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1836 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1863 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); in mlx4_INIT_HCA()
1864 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1866 MLX4_PUT(inbox, param->log_mc_hash_sz, in mlx4_INIT_HCA()
1868 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1877 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1878 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); in mlx4_INIT_HCA()
1879 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); in mlx4_INIT_HCA()
1880 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); in mlx4_INIT_HCA()
1881 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1885 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); in mlx4_INIT_HCA()
1886 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); in mlx4_INIT_HCA()
1905 struct mlx4_init_hca_param *param) in mlx4_QUERY_HCA() argument
1934 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); in mlx4_QUERY_HCA()
1935 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); in mlx4_QUERY_HCA()
1939 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); in mlx4_QUERY_HCA()
1940 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); in mlx4_QUERY_HCA()
1941 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1942 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); in mlx4_QUERY_HCA()
1943 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1944 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); in mlx4_QUERY_HCA()
1945 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); in mlx4_QUERY_HCA()
1946 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); in mlx4_QUERY_HCA()
1947 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1948 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); in mlx4_QUERY_HCA()
1949 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); in mlx4_QUERY_HCA()
1950 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); in mlx4_QUERY_HCA()
1951 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); in mlx4_QUERY_HCA()
1955 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; in mlx4_QUERY_HCA()
1959 param->steering_mode = MLX4_STEERING_MODE_B0; in mlx4_QUERY_HCA()
1961 param->steering_mode = MLX4_STEERING_MODE_A0; in mlx4_QUERY_HCA()
1965 param->rss_ip_frags = 1; in mlx4_QUERY_HCA()
1968 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_QUERY_HCA()
1969 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); in mlx4_QUERY_HCA()
1970 MLX4_GET(param->log_mc_entry_sz, outbox, in mlx4_QUERY_HCA()
1972 MLX4_GET(param->log_mc_table_sz, outbox, in mlx4_QUERY_HCA()
1976 param->dmfs_high_steer_mode = in mlx4_QUERY_HCA()
1979 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); in mlx4_QUERY_HCA()
1980 MLX4_GET(param->log_mc_entry_sz, outbox, in mlx4_QUERY_HCA()
1982 MLX4_GET(param->log_mc_hash_sz, outbox, in mlx4_QUERY_HCA()
1984 MLX4_GET(param->log_mc_table_sz, outbox, in mlx4_QUERY_HCA()
1991 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; in mlx4_QUERY_HCA()
1993 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; in mlx4_QUERY_HCA()
1998 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; in mlx4_QUERY_HCA()
1999 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; in mlx4_QUERY_HCA()
2000 param->cqe_size = 1 << ((byte_field & in mlx4_QUERY_HCA()
2002 param->eqe_size = 1 << (((byte_field & in mlx4_QUERY_HCA()
2008 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); in mlx4_QUERY_HCA()
2009 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); in mlx4_QUERY_HCA()
2010 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); in mlx4_QUERY_HCA()
2011 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); in mlx4_QUERY_HCA()
2012 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); in mlx4_QUERY_HCA()
2016 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); in mlx4_QUERY_HCA()
2017 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); in mlx4_QUERY_HCA()
2022 param->phv_check_en = 1; in mlx4_QUERY_HCA()