Lines Matching refs:__le32
53 __le32 reserved[4];
58 __le32 reserved[4];
63 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
64 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
68 __le32 reserved0[55] /* Pad to 15 cycles */;
293 __le32 reg0 /* reg0 */;
294 __le32 reg1 /* reg1 */;
295 __le32 reg2 /* reg2 */;
296 __le32 reg3 /* reg3 */;
297 __le32 reg4 /* reg4 */;
298 __le32 reg5 /* cf_array0 */;
299 __le32 reg6 /* cf_array1 */;
304 __le32 reg7 /* reg7 */;
305 __le32 reg8 /* reg8 */;
306 __le32 reg9 /* reg9 */;
318 __le32 reg10 /* reg10 */;
319 __le32 reg11 /* reg11 */;
320 __le32 reg12 /* reg12 */;
321 __le32 reg13 /* reg13 */;
322 __le32 reg14 /* reg14 */;
323 __le32 reg15 /* reg15 */;
324 __le32 reg16 /* reg16 */;
325 __le32 reg17 /* reg17 */;
326 __le32 reg18 /* reg18 */;
327 __le32 reg19 /* reg19 */;
336 __le32 reserved[24];
341 __le32 reserved[4];
391 __le32 reserved[2] /* Reserved */;
461 __le32 cid /* Slowpath Connection CID */;
489 __le32 atten_bits;
490 __le32 atten_ack;
493 __le32 reserved1;
669 __le32 opcode;
708 __le32 src_addr_lo;
709 __le32 src_addr_hi;
710 __le32 dst_addr_lo;
711 __le32 dst_addr_hi;
718 __le32 comp_addr_lo /* PCIe completion address low or grc address */;
719 __le32 comp_addr_hi;
720 __le32 comp_val /* Value to write to copmletion address */;
721 __le32 crc32 /* crc16 result */;
722 __le32 crc_32_c /* crc32_c result */;
732 __le32 sb_id_and_flags;
741 __le32 reserved1;
761 __le32 igu_mapping_line_fields;
778 __le32 data;
779 __le32 msix_vector_fields;
852 __le32 reg0 /* reg0 */;
853 __le32 reg1 /* reg1 */;
950 __le32 command;
1042 __le32 reg0 /* reg0 */;
1043 __le32 reg1 /* reg1 */;
1044 __le32 reg2 /* reg2 */;
1045 __le32 reg3 /* reg3 */;
1046 __le32 reg4 /* reg4 */;
1047 __le32 reg5 /* reg5 */;
1048 __le32 reg6 /* reg6 */;
1049 __le32 reg7 /* reg7 */;
1050 __le32 reg8 /* reg8 */;
1059 __le32 reg9 /* reg9 */;
1060 __le32 reg10 /* reg10 */;
1124 __le32 rx_producers /* reg0 */;
1125 __le32 reg1 /* reg1 */;
1126 __le32 reg2 /* reg2 */;
1127 __le32 reg3 /* reg3 */;
1166 __le32 reg0 /* reg0 */;
1167 __le32 reg1 /* reg1 */;
1172 __le32 reg2 /* reg2 */;
1173 __le32 reg3 /* reg3 */;
1285 __le32 data;
1293 __le32 data;
1301 __le32 data;
1309 __le32 data;
1334 __le32 op_data;
1353 __le32 op_data;
1358 __le32 delay /* delay in us */;
1363 __le32 op_data;
1376 __le32 op_data;
1385 __le32 phase_data;
1404 __le32 op_data;
1409 __le32 param2 /* Init param 2 */;
1420 __le32 inline_val;
1421 __le32 zeros_count;
1422 __le32 array_offset;
1428 __le32 data;
1444 __le32 op_data;
1455 __le32 expected_val;
2289 __le32 reserved[4];
2294 __le32 reserved[8];
2299 __le32 reserved[60];
2524 __le32 reg0 /* reg0 */;
2525 __le32 reg1 /* reg1 */;
2526 __le32 reg2 /* reg2 */;
2527 __le32 reg3 /* reg3 */;
2528 __le32 reg4 /* reg4 */;
2529 __le32 reg5 /* cf_array0 */;
2530 __le32 reg6 /* cf_array1 */;
2535 __le32 reg7 /* reg7 */;
2536 __le32 reg8 /* reg8 */;
2537 __le32 reg9 /* reg9 */;
2549 __le32 reg10 /* reg10 */;
2550 __le32 reg11 /* reg11 */;
2551 __le32 reg12 /* reg12 */;
2552 __le32 reg13 /* reg13 */;
2553 __le32 reg14 /* reg14 */;
2554 __le32 reg15 /* reg15 */;
2555 __le32 reg16 /* reg16 */;
2556 __le32 reg17 /* reg17 */;
2557 __le32 reg18 /* reg18 */;
2558 __le32 reg19 /* reg19 */;
2567 __le32 reserved[4];
2572 __le32 reserved[8];
2577 __le32 reserved[40];
2606 __le32 vni;
2684 __le32 reserved2[2];
2686 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2687 __le32 reserved3[2];
2876 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
2921 __le32 reg0 /* reg0 */;
2922 __le32 reg1 /* reg1 */;
3008 __le32 reg0 /* reg0 */;
3009 __le32 reg1 /* reg1 */;
3010 __le32 reg2 /* reg2 */;
3011 __le32 reg3 /* reg3 */;
3012 __le32 reg4 /* reg4 */;
3013 __le32 reg5 /* reg5 */;
3014 __le32 reg6 /* reg6 */;
3015 __le32 reg7 /* reg7 */;
3016 __le32 reg8 /* reg8 */;
3025 __le32 reg9 /* reg9 */;
3026 __le32 reg10 /* reg10 */;
3090 __le32 reg0 /* reg0 */;
3091 __le32 reg1 /* reg1 */;
3092 __le32 reg2 /* reg2 */;
3093 __le32 reg3 /* reg3 */;