55 #define SMC_IO_SHIFT		(lp->io_shift)
186 #define SMC_IO_SHIFT		(lp->io_shift)
275 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
277 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)  in smc_pxa_dma_inpump()  argument
285 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
286 	tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,  in smc_pxa_dma_inpump()
290 		dma_async_issue_pending(lp->dma_chan);  in smc_pxa_dma_inpump()
292 			status = dmaengine_tx_status(lp->dma_chan, cookie,  in smc_pxa_dma_inpump()
297 		dmaengine_terminate_all(lp->dma_chan);  in smc_pxa_dma_inpump()
299 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
303 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,  in smc_pxa_dma_insl()  argument
310 	if (!lp->dma_chan) {  in smc_pxa_dma_insl()
325 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
326 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
329 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insl()
331 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insl()
337 	smc_pxa_dma_inpump(lp, buf, len);  in smc_pxa_dma_insl()
344 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
346 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,  in smc_pxa_dma_insw()  argument
353 	if (!lp->dma_chan) {  in smc_pxa_dma_insw()
368 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
369 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
372 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insw()
374 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insw()
380 	smc_pxa_dma_inpump(lp, buf, len);  in smc_pxa_dma_insw()
481 #define TCR_REG(lp) 	SMC_REG(lp, 0x0000, 0)  argument
500 #define EPH_STATUS_REG(lp)	SMC_REG(lp, 0x0002, 0)  argument
519 #define RCR_REG(lp)		SMC_REG(lp, 0x0004, 0)  argument
536 #define COUNTER_REG(lp)	SMC_REG(lp, 0x0006, 0)  argument
541 #define MIR_REG(lp)		SMC_REG(lp, 0x0008, 0)  argument
546 #define RPC_REG(lp)		SMC_REG(lp, 0x000A, 0)  argument
572 #define CONFIG_REG(lp)	SMC_REG(lp, 0x0000,	1)  argument
584 #define BASE_REG(lp)	SMC_REG(lp, 0x0002, 1)  argument
589 #define ADDR0_REG(lp)	SMC_REG(lp, 0x0004, 1)  argument
590 #define ADDR1_REG(lp)	SMC_REG(lp, 0x0006, 1)  argument
591 #define ADDR2_REG(lp)	SMC_REG(lp, 0x0008, 1)  argument
596 #define GP_REG(lp)		SMC_REG(lp, 0x000A, 1)  argument
601 #define CTL_REG(lp)		SMC_REG(lp, 0x000C, 1)  argument
614 #define MMU_CMD_REG(lp)	SMC_REG(lp, 0x0000, 2)  argument
628 #define PN_REG(lp)		SMC_REG(lp, 0x0002, 2)  argument
633 #define AR_REG(lp)		SMC_REG(lp, 0x0003, 2)  argument
639 #define TXFIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)  argument
644 #define RXFIFO_REG(lp)	SMC_REG(lp, 0x0005, 2)  argument
647 #define FIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)  argument
651 #define PTR_REG(lp)		SMC_REG(lp, 0x0006, 2)  argument
659 #define DATA_REG(lp)	SMC_REG(lp, 0x0008, 2)  argument
664 #define INT_REG(lp)		SMC_REG(lp, 0x000C, 2)  argument
669 #define IM_REG(lp)		SMC_REG(lp, 0x000D, 2)  argument
682 #define MCAST_REG1(lp)	SMC_REG(lp, 0x0000, 3)  argument
683 #define MCAST_REG2(lp)	SMC_REG(lp, 0x0002, 3)  argument
684 #define MCAST_REG3(lp)	SMC_REG(lp, 0x0004, 3)  argument
685 #define MCAST_REG4(lp)	SMC_REG(lp, 0x0006, 3)  argument
690 #define MII_REG(lp)		SMC_REG(lp, 0x0008, 3)  argument
701 #define REV_REG(lp)		SMC_REG(lp, 0x000A, 3)  argument
707 #define ERCV_REG(lp)	SMC_REG(lp, 0x000C, 3)  argument
714 #define EXT_REG(lp)		SMC_REG(lp, 0x0000, 7)  argument
838 #define SMC_REG(lp, reg, bank)					\  argument
840 		int __b = SMC_CURRENT_BANK(lp);			\
849 #define SMC_REG(lp, reg, bank)	(reg<<SMC_IO_SHIFT)  argument
861 #define SMC_MUST_ALIGN_WRITE(lp)	SMC_32BIT(lp)  argument
863 #define SMC_GET_PN(lp)						\  argument
864 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, PN_REG(lp)))	\
865 				: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
867 #define SMC_SET_PN(lp, x)						\  argument
869 		if (SMC_MUST_ALIGN_WRITE(lp))				\
870 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));	\
871 		else if (SMC_8BIT(lp))				\
872 			SMC_outb(x, ioaddr, PN_REG(lp));		\
874 			SMC_outw(x, ioaddr, PN_REG(lp));		\
877 #define SMC_GET_AR(lp)						\  argument
878 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, AR_REG(lp)))	\
879 				: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
881 #define SMC_GET_TXFIFO(lp)						\  argument
882 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, TXFIFO_REG(lp)))	\
883 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
885 #define SMC_GET_RXFIFO(lp)						\  argument
886 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, RXFIFO_REG(lp)))	\
887 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
889 #define SMC_GET_INT(lp)						\  argument
890 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, INT_REG(lp)))	\
891 				: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
893 #define SMC_ACK_INT(lp, x)						\  argument
895 		if (SMC_8BIT(lp))					\
896 			SMC_outb(x, ioaddr, INT_REG(lp));		\
901 			__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
902 			SMC_outw(__mask | (x), ioaddr, INT_REG(lp));	\
907 #define SMC_GET_INT_MASK(lp)						\  argument
908 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, IM_REG(lp)))	\
909 				: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
911 #define SMC_SET_INT_MASK(lp, x)					\  argument
913 		if (SMC_8BIT(lp))					\
914 			SMC_outb(x, ioaddr, IM_REG(lp));		\
916 			SMC_outw((x) << 8, ioaddr, INT_REG(lp));	\
919 #define SMC_CURRENT_BANK(lp)	SMC_inw(ioaddr, BANK_SELECT)  argument
921 #define SMC_SELECT_BANK(lp, x)					\  argument
923 		if (SMC_MUST_ALIGN_WRITE(lp))				\
929 #define SMC_GET_BASE(lp)		SMC_inw(ioaddr, BASE_REG(lp))  argument
931 #define SMC_SET_BASE(lp, x)		SMC_outw(x, ioaddr, BASE_REG(lp))  argument
933 #define SMC_GET_CONFIG(lp)	SMC_inw(ioaddr, CONFIG_REG(lp))  argument
935 #define SMC_SET_CONFIG(lp, x)	SMC_outw(x, ioaddr, CONFIG_REG(lp))  argument
937 #define SMC_GET_COUNTER(lp)	SMC_inw(ioaddr, COUNTER_REG(lp))  argument
939 #define SMC_GET_CTL(lp)		SMC_inw(ioaddr, CTL_REG(lp))  argument
941 #define SMC_SET_CTL(lp, x)		SMC_outw(x, ioaddr, CTL_REG(lp))  argument
943 #define SMC_GET_MII(lp)		SMC_inw(ioaddr, MII_REG(lp))  argument
945 #define SMC_GET_GP(lp)		SMC_inw(ioaddr, GP_REG(lp))  argument
947 #define SMC_SET_GP(lp, x)						\  argument
949 		if (SMC_MUST_ALIGN_WRITE(lp))				\
950 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));	\
952 			SMC_outw(x, ioaddr, GP_REG(lp));		\
955 #define SMC_SET_MII(lp, x)		SMC_outw(x, ioaddr, MII_REG(lp))  argument
957 #define SMC_GET_MIR(lp)		SMC_inw(ioaddr, MIR_REG(lp))  argument
959 #define SMC_SET_MIR(lp, x)		SMC_outw(x, ioaddr, MIR_REG(lp))  argument
961 #define SMC_GET_MMU_CMD(lp)	SMC_inw(ioaddr, MMU_CMD_REG(lp))  argument
963 #define SMC_SET_MMU_CMD(lp, x)	SMC_outw(x, ioaddr, MMU_CMD_REG(lp))  argument
965 #define SMC_GET_FIFO(lp)		SMC_inw(ioaddr, FIFO_REG(lp))  argument
967 #define SMC_GET_PTR(lp)		SMC_inw(ioaddr, PTR_REG(lp))  argument
969 #define SMC_SET_PTR(lp, x)						\  argument
971 		if (SMC_MUST_ALIGN_WRITE(lp))				\
972 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));	\
974 			SMC_outw(x, ioaddr, PTR_REG(lp));		\
977 #define SMC_GET_EPH_STATUS(lp)	SMC_inw(ioaddr, EPH_STATUS_REG(lp))  argument
979 #define SMC_GET_RCR(lp)		SMC_inw(ioaddr, RCR_REG(lp))  argument
981 #define SMC_SET_RCR(lp, x)		SMC_outw(x, ioaddr, RCR_REG(lp))  argument
983 #define SMC_GET_REV(lp)		SMC_inw(ioaddr, REV_REG(lp))  argument
985 #define SMC_GET_RPC(lp)		SMC_inw(ioaddr, RPC_REG(lp))  argument
987 #define SMC_SET_RPC(lp, x)						\  argument
989 		if (SMC_MUST_ALIGN_WRITE(lp))				\
990 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));	\
992 			SMC_outw(x, ioaddr, RPC_REG(lp));		\
995 #define SMC_GET_TCR(lp)		SMC_inw(ioaddr, TCR_REG(lp))  argument
997 #define SMC_SET_TCR(lp, x)		SMC_outw(x, ioaddr, TCR_REG(lp))  argument
1000 #define SMC_GET_MAC_ADDR(lp, addr)					\  argument
1003 		__v = SMC_inw(ioaddr, ADDR0_REG(lp));			\
1005 		__v = SMC_inw(ioaddr, ADDR1_REG(lp));			\
1007 		__v = SMC_inw(ioaddr, ADDR2_REG(lp));			\
1012 #define SMC_SET_MAC_ADDR(lp, addr)					\  argument
1014 		SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1015 		SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1016 		SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1019 #define SMC_SET_MCAST(lp, x)						\  argument
1022 		SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1023 		SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1024 		SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1025 		SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1028 #define SMC_PUT_PKT_HDR(lp, status, length)				\  argument
1030 		if (SMC_32BIT(lp))					\
1032 				 DATA_REG(lp));			\
1034 			SMC_outw(status, ioaddr, DATA_REG(lp));	\
1035 			SMC_outw(length, ioaddr, DATA_REG(lp));	\
1039 #define SMC_GET_PKT_HDR(lp, status, length)				\  argument
1041 		if (SMC_32BIT(lp)) {				\
1042 			unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1046 			(status) = SMC_inw(ioaddr, DATA_REG(lp));	\
1047 			(length) = SMC_inw(ioaddr, DATA_REG(lp));	\
1051 #define SMC_PUSH_DATA(lp, p, l)					\  argument
1053 		if (SMC_32BIT(lp)) {				\
1059 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1062 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1063 				__ioaddr = lp->datacs;			\
1064 			SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1067 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1069 		} else if (SMC_16BIT(lp))				\
1070 			SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1071 		else if (SMC_8BIT(lp))				\
1072 			SMC_outsb(ioaddr, DATA_REG(lp), p, l);	\
1075 #define SMC_PULL_DATA(lp, p, l)					\  argument
1077 		if (SMC_32BIT(lp)) {				\
1097 				SMC_SET_PTR(lp,			\
1100 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1101 				__ioaddr = lp->datacs;			\
1103 			SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1104 		} else if (SMC_16BIT(lp))				\
1105 			SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1106 		else if (SMC_8BIT(lp))				\
1107 			SMC_insb(ioaddr, DATA_REG(lp), p, l);		\