190 	u32 cr;  in axienet_dma_bd_init()  local
237 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_bd_init()
239 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |  in axienet_dma_bd_init()
242 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |  in axienet_dma_bd_init()
245 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_bd_init()
247 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_dma_bd_init()
250 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_bd_init()
252 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |  in axienet_dma_bd_init()
255 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |  in axienet_dma_bd_init()
258 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_bd_init()
260 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_dma_bd_init()
266 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_bd_init()
268 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_bd_init()
277 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_bd_init()
279 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_bd_init()
809 	u32 cr;  in axienet_tx_irq()  local
827 		cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_tx_irq()
829 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_tx_irq()
831 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_tx_irq()
833 		cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_tx_irq()
835 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_tx_irq()
837 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_tx_irq()
858 	u32 cr;  in axienet_rx_irq()  local
876 		cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_rx_irq()
878 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_rx_irq()
880 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_rx_irq()
882 		cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_rx_irq()
884 		cr &= (~XAXIDMA_IRQ_ALL_MASK);  in axienet_rx_irq()
886 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_rx_irq()
990 	u32 cr;  in axienet_stop()  local
995 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_stop()
997 			  cr & (~XAXIDMA_CR_RUNSTOP_MASK));  in axienet_stop()
998 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_stop()
1000 			  cr & (~XAXIDMA_CR_RUNSTOP_MASK));  in axienet_stop()
1369 	u32 cr, i;  in axienet_dma_err_handler()  local
1428 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_err_handler()
1430 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |  in axienet_dma_err_handler()
1433 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |  in axienet_dma_err_handler()
1436 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_err_handler()
1438 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);  in axienet_dma_err_handler()
1441 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_err_handler()
1443 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |  in axienet_dma_err_handler()
1446 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |  in axienet_dma_err_handler()
1449 	cr |= XAXIDMA_IRQ_ALL_MASK;  in axienet_dma_err_handler()
1451 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);  in axienet_dma_err_handler()
1457 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);  in axienet_dma_err_handler()
1459 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_err_handler()
1468 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);  in axienet_dma_err_handler()
1470 			  cr | XAXIDMA_CR_RUNSTOP_MASK);  in axienet_dma_err_handler()