Lines Matching refs:XEL_TSR_OFFSET
39 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ macro
161 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
163 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
187 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
189 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
326 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
339 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
357 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
359 __raw_writel(reg_data, addr + XEL_TSR_OFFSET); in xemaclite_send_data()
471 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_update_address()
472 __raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); in xemaclite_update_address()
475 while ((__raw_readl(addr + XEL_TSR_OFFSET) & in xemaclite_update_address()
653 tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET); in xemaclite_interrupt()
658 __raw_writel(tx_status, base_addr + XEL_TSR_OFFSET); in xemaclite_interrupt()
664 tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); in xemaclite_interrupt()
670 XEL_TSR_OFFSET); in xemaclite_interrupt()
1144 __raw_writel(0, lp->base_addr + XEL_TSR_OFFSET); in xemaclite_of_probe()
1145 __raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); in xemaclite_of_probe()