Lines Matching refs:b43_phy_mask
216 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF); in lpphy_baseband_rev0_1_init()
230 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE); in lpphy_baseband_rev0_1_init()
337 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev0_1_init()
339 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF); in lpphy_baseband_rev0_1_init()
340 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF); in lpphy_baseband_rev0_1_init()
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); in lpphy_baseband_rev2plus_init()
427 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); in lpphy_baseband_rev2plus_init()
441 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF); in lpphy_baseband_rev2plus_init()
475 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev2plus_init()
477 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40); in lpphy_baseband_rev2plus_init()
684 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD); in lpphy_radio_init()
769 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); in lpphy_disable_crs()
771 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); in lpphy_disable_crs()
775 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF); in lpphy_disable_crs()
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF); in lpphy_disable_crs()
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F); in lpphy_disable_crs()
783 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF); in lpphy_disable_crs()
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF); in lpphy_disable_crs()
788 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF); in lpphy_disable_crs()
797 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80); in lpphy_restore_crs()
798 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00); in lpphy_restore_crs()
805 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE); in lpphy_disable_rx_gain_override()
806 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF); in lpphy_disable_rx_gain_override()
807 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF); in lpphy_disable_rx_gain_override()
809 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_rx_gain_override()
811 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF); in lpphy_disable_rx_gain_override()
812 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7); in lpphy_disable_rx_gain_override()
815 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF); in lpphy_disable_rx_gain_override()
838 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_tx_gain_override()
840 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F); in lpphy_disable_tx_gain_override()
841 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF); in lpphy_disable_tx_gain_override()
843 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF); in lpphy_disable_tx_gain_override()
979 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD); in lpphy_stop_ddfs()
980 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF); in lpphy_stop_ddfs()
987 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80); in lpphy_run_ddfs()
988 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF); in lpphy_run_ddfs()
994 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB); in lpphy_run_ddfs()
1004 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7); in lpphy_rx_iq_est()
1007 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF); in lpphy_rx_iq_est()
1048 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_loopback()
1176 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD); in lpphy_set_tx_power_control()
1435 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF); in b43_lpphy_op_software_rfkill()
1437 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF); in b43_lpphy_op_software_rfkill()
1438 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF); in b43_lpphy_op_software_rfkill()
1441 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1443 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF); in b43_lpphy_op_software_rfkill()
1447 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1449 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7); in b43_lpphy_op_software_rfkill()
1451 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7); in b43_lpphy_op_software_rfkill()
1478 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7); in lpphy_set_tssi_mux()
1506 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF); in lpphy_tx_pctl_init_hw()
1509 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE); in lpphy_tx_pctl_init_hw()
1516 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF); in lpphy_tx_pctl_init_hw()
1521 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF); in lpphy_tx_pctl_init_hw()
1528 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1541 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1720 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF); in lpphy_calc_rx_iq_comp()
1819 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000); in lpphy_stop_tx_tone()
1927 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1928 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_rx_iq_cal()
1940 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC); in lpphy_rx_iq_cal()
1941 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7); in lpphy_rx_iq_cal()
1942 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF); in lpphy_rx_iq_cal()
1950 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1951 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF); in lpphy_rx_iq_cal()
2687 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8); in b43_lpphy_op_switch_analog()