Lines Matching refs:rtl8xxxu_write32
1070 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) in rtl8xxxu_write32() function
1144 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); in rtl8xxxu_read_rfreg()
1148 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); in rtl8xxxu_read_rfreg()
1152 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); in rtl8xxxu_read_rfreg()
1183 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); in rtl8xxxu_write_rfreg()
1233 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); in rtl8723a_h2c_cmd()
1260 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); in rtl8723a_enable_rf()
1270 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8723a_enable_rf()
1274 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723a_enable_rf()
1277 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); in rtl8723a_enable_rf()
1279 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); in rtl8723a_enable_rf()
1302 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); in rtl8723a_disable_rf()
1307 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8723a_disable_rf()
1312 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723a_disable_rf()
1316 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); in rtl8723a_disable_rf()
1318 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); in rtl8723a_disable_rf()
1390 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723au_config_channel()
1394 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8723au_config_channel()
1398 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); in rtl8723au_config_channel()
1417 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); in rtl8723au_config_channel()
1421 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723au_config_channel()
1425 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8723au_config_channel()
1435 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8723au_config_channel()
1443 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8723au_config_channel()
1447 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); in rtl8723au_config_channel()
1455 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8723au_config_channel()
1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723a_set_tx_power()
1545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723a_set_tx_power()
1550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723a_set_tx_power()
1555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8723a_set_tx_power()
1561 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a); in rtl8723a_set_tx_power()
1562 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b); in rtl8723a_set_tx_power()
1564 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a); in rtl8723a_set_tx_power()
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b); in rtl8723a_set_tx_power()
1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a); in rtl8723a_set_tx_power()
1573 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b); in rtl8723a_set_tx_power()
1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a); in rtl8723a_set_tx_power()
1576 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b); in rtl8723a_set_tx_power()
1578 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a); in rtl8723a_set_tx_power()
1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b); in rtl8723a_set_tx_power()
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a); in rtl8723a_set_tx_power()
1589 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b); in rtl8723a_set_tx_power()
1943 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); in rtl8xxxu_read_efuse()
2068 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); in rtl8xxxu_start_firmware()
2111 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19)); in rtl8xxxu_download_firmware()
2313 ret = rtl8xxxu_write32(priv, reg, val); in rtl8xxxu_init_phy_regs()
2356 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8xxxu_init_phy_bb()
2383 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); in rtl8xxxu_init_phy_bb()
2388 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); in rtl8xxxu_init_phy_bb()
2393 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8xxxu_init_phy_bb()
2399 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8xxxu_init_phy_bb()
2404 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); in rtl8xxxu_init_phy_bb()
2409 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); in rtl8xxxu_init_phy_bb()
2414 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); in rtl8xxxu_init_phy_bb()
2419 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); in rtl8xxxu_init_phy_bb()
2424 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); in rtl8xxxu_init_phy_bb()
2429 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); in rtl8xxxu_init_phy_bb()
2445 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); in rtl8xxxu_init_phy_bb()
2454 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); in rtl8xxxu_init_phy_bb()
2542 rtl8xxxu_write32(priv, reg_int_oe, val32); in rtl8xxxu_init_phy_rf()
2547 rtl8xxxu_write32(priv, reg_int_oe, val32); in rtl8xxxu_init_phy_rf()
2555 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); in rtl8xxxu_init_phy_rf()
2560 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); in rtl8xxxu_init_phy_rf()
2582 rtl8xxxu_write32(priv, REG_LLT_INIT, value); in rtl8xxxu_llt_write()
2767 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2773 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_a()
2783 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2788 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2794 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_a()
2806 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2813 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2820 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); in rtl8xxxu_fill_iqk_matrix_a()
2845 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2851 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_b()
2861 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2866 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2872 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_b()
2884 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2891 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2898 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2976 rtl8xxxu_write32(priv, reg[i], backup[i]); in rtl8xxxu_restore_mac_regs()
2994 rtl8xxxu_write32(priv, regs[i], backup[i]); in rtl8xxxu_restore_regs()
3007 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0); in rtl8xxxu_path_adda_on()
3009 rtl8xxxu_write32(priv, regs[0], path_on); in rtl8xxxu_path_adda_on()
3013 rtl8xxxu_write32(priv, regs[i], path_on); in rtl8xxxu_path_adda_on()
3035 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); in rtl8xxxu_iqk_path_a()
3036 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); in rtl8xxxu_iqk_path_a()
3037 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); in rtl8xxxu_iqk_path_a()
3042 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); in rtl8xxxu_iqk_path_a()
3046 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); in rtl8xxxu_iqk_path_a()
3047 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); in rtl8xxxu_iqk_path_a()
3048 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); in rtl8xxxu_iqk_path_a()
3049 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); in rtl8xxxu_iqk_path_a()
3053 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); in rtl8xxxu_iqk_path_a()
3056 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8xxxu_iqk_path_a()
3057 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8xxxu_iqk_path_a()
3092 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); in rtl8xxxu_iqk_path_b()
3093 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); in rtl8xxxu_iqk_path_b()
3174 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); in rtl8xxxu_phy_iqcalibrate()
3175 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); in rtl8xxxu_phy_iqcalibrate()
3180 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_phy_iqcalibrate()
3182 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8xxxu_phy_iqcalibrate()
3183 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8xxxu_phy_iqcalibrate()
3184 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8xxxu_phy_iqcalibrate()
3188 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8xxxu_phy_iqcalibrate()
3192 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
3195 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
3198 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); in rtl8xxxu_phy_iqcalibrate()
3199 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); in rtl8xxxu_phy_iqcalibrate()
3206 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); in rtl8xxxu_phy_iqcalibrate()
3209 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); in rtl8xxxu_phy_iqcalibrate()
3212 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3213 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8xxxu_phy_iqcalibrate()
3214 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8xxxu_phy_iqcalibrate()
3253 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); in rtl8xxxu_phy_iqcalibrate()
3254 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); in rtl8xxxu_phy_iqcalibrate()
3255 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3286 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); in rtl8xxxu_phy_iqcalibrate()
3295 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); in rtl8xxxu_phy_iqcalibrate()
3296 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); in rtl8xxxu_phy_iqcalibrate()
3311 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); in rtl8xxxu_phy_iqcalibrate()
3314 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, in rtl8xxxu_phy_iqcalibrate()
3319 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8xxxu_phy_iqcalibrate()
3320 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8xxxu_phy_iqcalibrate()
3435 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8723a_phy_lc_calibrate()
3468 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); in rtl8723a_phy_lc_calibrate()
3725 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8xxxu_emu_to_active()
3821 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); in rtl8723au_power_on()
3926 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8192cu_power_on()
3945 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8xxxu_power_off()
4076 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); in rtl8xxxu_init_device()
4077 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8xxxu_init_device()
4078 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); in rtl8xxxu_init_device()
4079 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8xxxu_init_device()
4082 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); in rtl8xxxu_init_device()
4088 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8xxxu_init_device()
4090 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210); in rtl8xxxu_init_device()
4111 rtl8xxxu_write32(priv, REG_RQPN, val32); in rtl8xxxu_init_device()
4148 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); in rtl8xxxu_init_device()
4149 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); in rtl8xxxu_init_device()
4161 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_init_device()
4166 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); in rtl8xxxu_init_device()
4167 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); in rtl8xxxu_init_device()
4175 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_init_device()
4194 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); in rtl8xxxu_init_device()
4195 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); in rtl8xxxu_init_device()
4196 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); in rtl8xxxu_init_device()
4197 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); in rtl8xxxu_init_device()
4200 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); in rtl8xxxu_init_device()
4201 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); in rtl8xxxu_init_device()
4202 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); in rtl8xxxu_init_device()
4203 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); in rtl8xxxu_init_device()
4227 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_init_device()
4232 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); in rtl8xxxu_init_device()
4247 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); in rtl8xxxu_init_device()
4274 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); in rtl8xxxu_init_device()
4322 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_init_device()
4328 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); in rtl8xxxu_init_device()
4374 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); in rtl8xxxu_cam_write()
4376 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); in rtl8xxxu_cam_write()
4433 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_set_basic_rates()
4493 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_bss_info_changed()
4511 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_bss_info_changed()
4533 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_bss_info_changed()
5143 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); in rtl8xxxu_submit_int_urb()
5254 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); in rtl8xxxu_conf_tx()
5258 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); in rtl8xxxu_conf_tx()
5262 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); in rtl8xxxu_conf_tx()
5266 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); in rtl8xxxu_conf_tx()
5363 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); in rtl8xxxu_set_key()
5366 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); in rtl8xxxu_set_key()
5484 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); in rtl8xxxu_start()
5522 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); in rtl8xxxu_stop()