Lines Matching refs:BIT
18 #define SYS_ISO_MD2PP BIT(0)
19 #define SYS_ISO_ANALOG_IPS BIT(5)
20 #define SYS_ISO_DIOR BIT(9)
21 #define SYS_ISO_PWC_EV25V BIT(14)
22 #define SYS_ISO_PWC_EV12V BIT(15)
25 #define SYS_FUNC_BBRSTB BIT(0)
26 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
27 #define SYS_FUNC_USBA BIT(2)
28 #define SYS_FUNC_UPLL BIT(3)
29 #define SYS_FUNC_USBD BIT(4)
30 #define SYS_FUNC_DIO_PCIE BIT(5)
31 #define SYS_FUNC_PCIEA BIT(6)
32 #define SYS_FUNC_PPLL BIT(7)
33 #define SYS_FUNC_PCIED BIT(8)
34 #define SYS_FUNC_DIOE BIT(9)
35 #define SYS_FUNC_CPU_ENABLE BIT(10)
36 #define SYS_FUNC_DCORE BIT(11)
37 #define SYS_FUNC_ELDR BIT(12)
38 #define SYS_FUNC_DIO_RF BIT(13)
39 #define SYS_FUNC_HWPDN BIT(14)
40 #define SYS_FUNC_MREGEN BIT(15)
43 #define APS_FSMCO_PFM_ALDN BIT(1)
44 #define APS_FSMCO_PFM_WOWL BIT(3)
45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
46 #define APS_FSMCO_MAC_ENABLE BIT(8)
47 #define APS_FSMCO_MAC_OFF BIT(9)
48 #define APS_FSMCO_HW_SUSPEND BIT(11)
49 #define APS_FSMCO_PCIE BIT(12)
50 #define APS_FSMCO_HW_POWERDOWN BIT(15)
51 #define APS_FSMCO_WLON_RESET BIT(16)
54 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
55 #define SYS_CLK_ANA8M BIT(1)
56 #define SYS_CLK_MACSLP BIT(4)
57 #define SYS_CLK_LOADER_ENABLE BIT(5)
58 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
59 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
60 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
61 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
62 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
63 #define SYS_CLK_ENABLE BIT(12)
64 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
67 #define EEPROM_BOOT BIT(4)
68 #define EEPROM_ENABLE BIT(5)
77 #define RF_ENABLE BIT(0)
78 #define RF_RSTB BIT(1)
79 #define RF_SDMRSTB BIT(2)
82 #define LDOA15_ENABLE BIT(0)
83 #define LDOA15_STANDBY BIT(1)
84 #define LDOA15_OBUF BIT(2)
85 #define LDOA15_REG_VOS BIT(3)
89 #define LDOV12D_ENABLE BIT(0)
90 #define LDOV12D_STANDBY BIT(1)
96 #define LPLDO_HSM BIT(2)
97 #define LPLDO_LSM_DIS BIT(3)
100 #define AFE_XTAL_ENABLE BIT(0)
101 #define AFE_XTAL_B_SELECT BIT(1)
102 #define AFE_XTAL_GATE_USB BIT(8)
103 #define AFE_XTAL_GATE_AFE BIT(11)
104 #define AFE_XTAL_RF_GATE BIT(14)
105 #define AFE_XTAL_GATE_DIG BIT(17)
106 #define AFE_XTAL_BT_GATE BIT(20)
109 #define AFE_PLL_ENABLE BIT(0)
110 #define AFE_PLL_320_ENABLE BIT(1)
111 #define APE_PLL_FREF_SELECT BIT(2)
112 #define AFE_PLL_EDGE_SELECT BIT(3)
113 #define AFE_PLL_WDOGB BIT(4)
114 #define AFE_PLL_LPF_ENABLE BIT(5)
120 #define EFUSE_TRPT BIT(7)
122 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
123 #define EFUSE_LDOE25_ENABLE BIT(31)
144 #define LEDCFG2_DPDT_SELECT BIT(7)
159 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
161 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
163 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
165 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
167 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
169 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
171 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
172 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
174 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
176 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
178 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
181 #define MCU_FW_DL_ENABLE BIT(0)
182 #define MCU_FW_DL_READY BIT(1)
183 #define MCU_FW_DL_CSUM_REPORT BIT(2)
184 #define MCU_MAC_INIT_READY BIT(3)
185 #define MCU_BB_INIT_READY BIT(4)
186 #define MCU_RF_INIT_READY BIT(5)
187 #define MCU_WINT_INIT_READY BIT(6)
188 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
189 #define MCU_CP_RESET BIT(23)
206 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
207 #define HPON_FSM_BONDING_1T2R BIT(22)
209 #define SYS_CFG_XCLK_VLD BIT(0)
210 #define SYS_CFG_ACLK_VLD BIT(1)
211 #define SYS_CFG_UCLK_VLD BIT(2)
212 #define SYS_CFG_PCLK_VLD BIT(3)
213 #define SYS_CFG_PCIRSTB BIT(4)
214 #define SYS_CFG_V15_VLD BIT(5)
215 #define SYS_CFG_TRP_B15V_EN BIT(7)
216 #define SYS_CFG_SIC_IDLE BIT(8)
217 #define SYS_CFG_BD_MAC2 BIT(9)
218 #define SYS_CFG_BD_MAC1 BIT(10)
219 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
220 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
221 #define SYS_CFG_BT_FUNC BIT(16)
222 #define SYS_CFG_VENDOR_ID BIT(19)
223 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
224 #define SYS_CFG_TRP_VAUX_EN BIT(23)
225 #define SYS_CFG_TRP_BT_EN BIT(24)
226 #define SYS_CFG_BD_PKG_SEL BIT(25)
227 #define SYS_CFG_BD_HCI_SEL BIT(26)
228 #define SYS_CFG_TYPE_ID BIT(27)
229 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
231 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
237 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
238 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
239 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
240 #define GPIO_PKG_SEL_HCI BIT(6)
241 #define GPIO_FEN_GPS BIT(7)
242 #define GPIO_FEN_BT BIT(8)
243 #define GPIO_FEN_WL BIT(9)
244 #define GPIO_FEN_PCI BIT(10)
245 #define GPIO_FEN_USB BIT(11)
246 #define GPIO_BTRF_HWPDN_N BIT(12)
247 #define GPIO_WLRF_HWPDN_N BIT(13)
248 #define GPIO_PDN_BT_N BIT(14)
249 #define GPIO_PDN_GPS_N BIT(15)
250 #define GPIO_BT_CTL_HWPDN BIT(16)
251 #define GPIO_GPS_CTL_HWPDN BIT(17)
252 #define GPIO_PPHY_SUSB BIT(20)
253 #define GPIO_UPHY_SUSB BIT(21)
254 #define GPIO_PCI_SUSEN BIT(22)
255 #define GPIO_USB_SUSEN BIT(23)
256 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
260 #define CR_HCI_TXDMA_ENABLE BIT(0)
261 #define CR_HCI_RXDMA_ENABLE BIT(1)
262 #define CR_TXDMA_ENABLE BIT(2)
263 #define CR_RXDMA_ENABLE BIT(3)
264 #define CR_PROTOCOL_ENABLE BIT(4)
265 #define CR_SCHEDULE_ENABLE BIT(5)
266 #define CR_MAC_TX_ENABLE BIT(6)
267 #define CR_MAC_RX_ENABLE BIT(7)
268 #define CR_SW_BEACON_ENABLE BIT(8)
269 #define CR_SECURITY_ENABLE BIT(9)
270 #define CR_CALTIMER_ENABLE BIT(10)
348 #define RQPN_LOAD BIT(31)
376 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
377 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
402 #define RSR_1M BIT(0)
403 #define RSR_2M BIT(1)
404 #define RSR_5_5M BIT(2)
405 #define RSR_11M BIT(3)
406 #define RSR_6M BIT(4)
407 #define RSR_9M BIT(5)
408 #define RSR_12M BIT(6)
409 #define RSR_18M BIT(7)
410 #define RSR_24M BIT(8)
411 #define RSR_36M BIT(9)
412 #define RSR_48M BIT(10)
413 #define RSR_54M BIT(11)
414 #define RSR_MCS0 BIT(12)
415 #define RSR_MCS1 BIT(13)
416 #define RSR_MCS2 BIT(14)
417 #define RSR_MCS3 BIT(15)
418 #define RSR_MCS4 BIT(16)
419 #define RSR_MCS5 BIT(17)
420 #define RSR_MCS6 BIT(18)
421 #define RSR_MCS7 BIT(19)
422 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
423 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
426 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
484 #define BEACON_ATIM BIT(0)
485 #define BEACON_CTRL_MBSSID BIT(1)
486 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
487 #define BEACON_FUNCTION_ENABLE BIT(3)
488 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
492 #define DUAL_TSF_RESET_TSF0 BIT(0)
493 #define DUAL_TSF_RESET_TSF1 BIT(1)
494 #define DUAL_TSF_RESET_P2P BIT(4)
495 #define DUAL_TSF_TX_OK BIT(5)
519 #define ACM_HW_CTRL_BK BIT(0)
520 #define ACM_HW_CTRL_BE BIT(1)
521 #define ACM_HW_CTRL_VI BIT(2)
522 #define ACM_HW_CTRL_VO BIT(3)
538 #define APSD_CTRL_OFF BIT(6)
539 #define APSD_CTRL_OFF_STATUS BIT(7)
541 #define BW_OPMODE_20MHZ BIT(2)
542 #define BW_OPMODE_5G BIT(1)
543 #define BW_OPMODE_11J BIT(0)
549 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
550 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
551 #define RCR_ACCEPT_MCAST BIT(2)
552 #define RCR_ACCEPT_BCAST BIT(3)
553 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
555 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
557 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
558 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
560 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
561 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
562 #define RCR_ACCEPT_DATA_FRAME BIT(11)
563 #define RCR_ACCEPT_CTRL_FRAME BIT(12)
564 #define RCR_ACCEPT_MGMT_FRAME BIT(13)
565 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
566 #define RCR_MFBEN BIT(22)
567 #define RCR_LSIGEN BIT(23)
568 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
569 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
570 #define RCR_APPEND_PHYSTAT BIT(28)
571 #define RCR_APPEND_ICV BIT(29)
572 #define RCR_APPEND_MIC BIT(30)
573 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
611 #define CAM_CMD_POLLING BIT(31)
612 #define CAM_CMD_WRITE BIT(16)
615 #define CAM_WRITE_VALID BIT(15)
619 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
620 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
621 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
622 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
623 #define SEC_CFG_SKBYA2 BIT(4)
624 #define SEC_CFG_NO_SKMC BIT(5)
625 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
626 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
648 #define FPGA_RF_MODE BIT(0)
649 #define FPGA_RF_MODE_JAPAN BIT(1)
650 #define FPGA_RF_MODE_CCK BIT(24)
651 #define FPGA_RF_MODE_OFDM BIT(25)
659 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
660 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
663 #define FPGA0_HSSI_PARM1_PI BIT(8)
671 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
672 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
693 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
694 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
707 #define FPGA0_RF_3WIRE_DATA BIT(0)
708 #define FPGA0_RF_3WIRE_CLOC BIT(1)
709 #define FPGA0_RF_3WIRE_LOAD BIT(2)
710 #define FPGA0_RF_3WIRE_RW BIT(3)
712 #define FPGA0_RF_RFENV BIT(4)
713 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
714 #define FPGA0_RF_TRSWB BIT(6)
715 #define FPGA0_RF_ANTSW BIT(8)
716 #define FPGA0_RF_ANTSWB BIT(9)
717 #define FPGA0_RF_PAPE BIT(10)
718 #define FPGA0_RF_PAPE5G BIT(11)
727 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
728 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
729 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
733 #define FPGA0_ANALOG2_20MHZ BIT(10)
747 #define CCK0_SIDEBAND BIT(4)
756 #define OFDM_RF_PATH_RX_A BIT(0)
757 #define OFDM_RF_PATH_RX_B BIT(1)
758 #define OFDM_RF_PATH_RX_C BIT(2)
759 #define OFDM_RF_PATH_RX_D BIT(3)
761 #define OFDM_RF_PATH_TX_A BIT(4)
762 #define OFDM_RF_PATH_TX_B BIT(5)
763 #define OFDM_RF_PATH_TX_C BIT(6)
764 #define OFDM_RF_PATH_TX_D BIT(7)
798 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
799 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
802 #define OFDM_LSTF_CONTINUE_TX BIT(28)
803 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
804 #define OFDM_LSTF_SINGLE_TONE BIT(30)
871 #define USB_HIMR_TIMEOUT2 BIT(31)
872 #define USB_HIMR_TIMEOUT1 BIT(30)
873 #define USB_HIMR_PSTIMEOUT BIT(29)
874 #define USB_HIMR_GTINT4 BIT(28)
875 #define USB_HIMR_GTINT3 BIT(27)
876 #define USB_HIMR_TXBCNERR BIT(26)
877 #define USB_HIMR_TXBCNOK BIT(25)
878 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
879 #define USB_HIMR_BCNDMAINT3 BIT(23)
880 #define USB_HIMR_BCNDMAINT2 BIT(22)
881 #define USB_HIMR_BCNDMAINT1 BIT(21)
882 #define USB_HIMR_BCNDMAINT0 BIT(20)
883 #define USB_HIMR_BCNDOK3 BIT(19)
884 #define USB_HIMR_BCNDOK2 BIT(18)
885 #define USB_HIMR_BCNDOK1 BIT(17)
886 #define USB_HIMR_BCNDOK0 BIT(16)
887 #define USB_HIMR_HSISR_IND BIT(15)
888 #define USB_HIMR_BCNDMAINT_E BIT(14)
890 #define USB_HIMR_CTW_END BIT(12)
892 #define USB_HIMR_C2HCMD BIT(10)
893 #define USB_HIMR_CPWM2 BIT(9)
894 #define USB_HIMR_CPWM BIT(8)
895 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
897 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
899 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
900 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
901 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
902 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
903 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
905 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
954 #define MODE_AG_CHANNEL_20MHZ BIT(10)