Lines Matching refs:rt2x00mmio_register_write
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
171 .write = rt2x00mmio_register_write,
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
280 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
298 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
305 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
336 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
343 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
350 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
357 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
364 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
368 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); in rt2400pci_config_erp()
373 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
378 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
383 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
392 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
514 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
534 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
537 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
541 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
570 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
642 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
649 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
665 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
670 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
675 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
693 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
698 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
705 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
776 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
788 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
794 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
800 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
805 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
811 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
820 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2400pci_init_registers()
821 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2400pci_init_registers()
822 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20); in rt2400pci_init_registers()
823 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2400pci_init_registers()
829 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
834 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
845 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
847 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000); in rt2400pci_init_registers()
854 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
863 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
865 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2400pci_init_registers()
870 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223); in rt2400pci_init_registers()
871 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2400pci_init_registers()
875 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
882 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
888 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
976 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
991 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
1024 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2400pci_disable_radio()
1043 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1056 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1183 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1207 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1323 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1350 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1383 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1422 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1636 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()