Lines Matching refs:rt2x00mmio_register_read
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); in rt61pci_mcu_request()
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_eepromregister_read()
208 .read = rt2x00mmio_register_read,
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_rfkill_poll()
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); in rt61pci_blink_set()
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); in rt61pci_config_shared_key()
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); in rt61pci_config_shared_key()
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); in rt61pci_config_pairwise_key()
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_filter()
556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_intf()
587 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_erp()
593 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_erp()
605 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_erp()
612 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_config_erp()
616 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); in rt61pci_config_erp()
713 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_config_antenna_2529_rx()
820 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); in rt61pci_config_ant()
927 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_retry_limit()
947 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
968 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
1014 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_link_stats()
1020 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_link_stats()
1139 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_start_queue()
1144 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_start_queue()
1162 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1167 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1172 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1177 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1193 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1198 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1203 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1208 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1213 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_stop_queue()
1218 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_stop_queue()
1300 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_load_firmware()
1339 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); in rt61pci_load_firmware()
1363 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1368 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1426 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); in rt61pci_init_queues()
1437 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); in rt61pci_init_queues()
1443 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); in rt61pci_init_queues()
1449 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); in rt61pci_init_queues()
1455 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); in rt61pci_init_queues()
1461 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); in rt61pci_init_queues()
1466 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); in rt61pci_init_queues()
1474 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); in rt61pci_init_queues()
1479 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); in rt61pci_init_queues()
1486 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); in rt61pci_init_queues()
1493 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_init_queues()
1504 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_init_registers()
1510 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); in rt61pci_init_registers()
1524 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); in rt61pci_init_registers()
1538 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); in rt61pci_init_registers()
1547 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); in rt61pci_init_registers()
1554 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); in rt61pci_init_registers()
1561 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_init_registers()
1574 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_init_registers()
1620 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_init_registers()
1621 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_init_registers()
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); in rt61pci_init_registers()
1627 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1632 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1637 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1723 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1726 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1736 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1744 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1784 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_enable_radio()
1807 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); in rt61pci_set_state()
1818 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®2); in rt61pci_set_state()
1977 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_write_beacon()
2038 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); in rt61pci_clear_beacon()
2174 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); in rt61pci_txdone()
2260 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_enable_interrupt()
2278 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_enable_mcu_interrupt()
2330 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); in rt61pci_interrupt()
2333 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_interrupt()
2371 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_interrupt()
2375 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_interrupt()
2395 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_validate_eeprom()
2513 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_init_eeprom()
2855 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_probe_hw()
2927 rt2x00mmio_register_read(rt2x00dev, offset, ®); in rt61pci_conf_tx()
2935 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); in rt61pci_conf_tx()
2939 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); in rt61pci_conf_tx()
2943 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); in rt61pci_conf_tx()
2956 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); in rt61pci_get_tsf()
2958 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); in rt61pci_get_tsf()