Lines Matching refs:REGISTERS_BASE
30 #define REGISTERS_BASE 0x00300000 macro
52 #define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
54 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
55 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
56 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
58 #define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
59 #define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
89 #define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
99 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
109 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
120 #define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
131 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
143 #define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
145 #define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538)
148 #define SOR_CFG (REGISTERS_BASE + 0x0800)
170 #define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
172 #define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808)
189 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
191 #define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
192 #define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
193 #define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
194 #define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0)
196 #define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
198 #define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674)
200 #define WL12XX_ENABLE (REGISTERS_BASE + 0x5450)
203 #define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
204 #define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808)
205 #define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
206 #define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
207 #define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
209 #define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
212 #define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608)
213 #define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C)
214 #define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610)
215 #define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614)
216 #define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618)
217 #define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
218 #define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
219 #define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624)
220 #define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
221 #define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
222 #define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630)
223 #define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634)
224 #define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638)
225 #define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C)
228 #define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994)
229 #define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998)
230 #define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C)
231 #define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0)
232 #define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4)
233 #define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8)
234 #define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC)
235 #define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0)
236 #define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420)
237 #define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424)
238 #define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428)
239 #define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C)
240 #define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430)
241 #define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434)
242 #define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438)
243 #define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C)
245 #define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
246 #define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
247 #define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)