Lines Matching refs:WL18XX_REGISTERS_BASE
25 #define WL18XX_REGISTERS_BASE 0x00800000 macro
45 #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
46 #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
47 #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
48 #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
49 #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
50 #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
51 #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
52 #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
53 #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
54 #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
55 #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
56 #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
57 #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
58 #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
60 #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
61 #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
62 #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
63 #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
64 #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
65 #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
67 #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
73 #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
74 #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
75 #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
76 #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
77 #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
78 #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
79 #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
80 #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
81 #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
82 #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
83 #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
84 #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
85 #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
86 #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
89 #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
90 #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
91 #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
92 #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
93 #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
94 #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
95 #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
96 #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
97 #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
98 #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
99 #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
100 #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
101 #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
102 #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
103 #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
104 #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
110 #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100)
111 #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C)