Lines Matching refs:DRV_BASE
27 #define DRV_BASE 0xb00 macro
207 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
208 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
209 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
210 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
211 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
212 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
213 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
214 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
215 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
216 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
217 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
218 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
219 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
220 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
221 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
222 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
223 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
232 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
233 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
234 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
235 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
236 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
237 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
238 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
239 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
240 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
241 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
242 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
243 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
244 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
245 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
258 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
259 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
260 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
261 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
268 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
269 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
270 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
271 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
272 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
273 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
274 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
275 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
276 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
277 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
278 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
279 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
280 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
281 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
282 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
283 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
284 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
285 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
286 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
287 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
288 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
289 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
296 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
297 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
298 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
299 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
300 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
301 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
302 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
303 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
304 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
305 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
306 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
307 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
308 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
309 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
310 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
311 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
312 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
313 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
314 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
315 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
316 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
317 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
318 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
319 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
320 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)