Lines Matching refs:nmk_chip
292 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_mode() argument
298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; in __nmk_gpio_set_mode()
299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; in __nmk_gpio_set_mode()
304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); in __nmk_gpio_set_mode()
305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); in __nmk_gpio_set_mode()
308 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_slpm() argument
314 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); in __nmk_gpio_set_slpm()
319 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); in __nmk_gpio_set_slpm()
322 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_pull() argument
328 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); in __nmk_gpio_set_pull()
331 nmk_chip->pull_up &= ~bit; in __nmk_gpio_set_pull()
336 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); in __nmk_gpio_set_pull()
339 nmk_chip->pull_up |= bit; in __nmk_gpio_set_pull()
340 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); in __nmk_gpio_set_pull()
342 nmk_chip->pull_up &= ~bit; in __nmk_gpio_set_pull()
343 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); in __nmk_gpio_set_pull()
347 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_lowemi() argument
351 bool enabled = nmk_chip->lowemi & bit; in __nmk_gpio_set_lowemi()
357 nmk_chip->lowemi |= bit; in __nmk_gpio_set_lowemi()
359 nmk_chip->lowemi &= ~bit; in __nmk_gpio_set_lowemi()
361 writel_relaxed(nmk_chip->lowemi, in __nmk_gpio_set_lowemi()
362 nmk_chip->addr + NMK_GPIO_LOWEMI); in __nmk_gpio_set_lowemi()
365 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_make_input() argument
368 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); in __nmk_gpio_make_input()
371 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_output() argument
375 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); in __nmk_gpio_set_output()
377 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); in __nmk_gpio_set_output()
380 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_make_output() argument
383 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); in __nmk_gpio_make_output()
384 __nmk_gpio_set_output(nmk_chip, offset, val); in __nmk_gpio_make_output()
387 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_mode_safe() argument
391 u32 rwimsc = nmk_chip->rwimsc; in __nmk_gpio_set_mode_safe()
392 u32 fwimsc = nmk_chip->fwimsc; in __nmk_gpio_set_mode_safe()
394 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()
398 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); in __nmk_gpio_set_mode_safe()
399 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); in __nmk_gpio_set_mode_safe()
401 nmk_chip->set_ioforce(true); in __nmk_gpio_set_mode_safe()
404 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); in __nmk_gpio_set_mode_safe()
406 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()
407 nmk_chip->set_ioforce(false); in __nmk_gpio_set_mode_safe()
409 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); in __nmk_gpio_set_mode_safe()
410 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); in __nmk_gpio_set_mode_safe()
415 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) in nmk_gpio_disable_lazy_irq() argument
417 u32 falling = nmk_chip->fimsc & BIT(offset); in nmk_gpio_disable_lazy_irq()
418 u32 rising = nmk_chip->rimsc & BIT(offset); in nmk_gpio_disable_lazy_irq()
419 int gpio = nmk_chip->chip.base + offset; in nmk_gpio_disable_lazy_irq()
420 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); in nmk_gpio_disable_lazy_irq()
430 nmk_chip->rimsc &= ~BIT(offset); in nmk_gpio_disable_lazy_irq()
431 writel_relaxed(nmk_chip->rimsc, in nmk_gpio_disable_lazy_irq()
432 nmk_chip->addr + NMK_GPIO_RIMSC); in nmk_gpio_disable_lazy_irq()
436 nmk_chip->fimsc &= ~BIT(offset); in nmk_gpio_disable_lazy_irq()
437 writel_relaxed(nmk_chip->fimsc, in nmk_gpio_disable_lazy_irq()
438 nmk_chip->addr + NMK_GPIO_FIMSC); in nmk_gpio_disable_lazy_irq()
441 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); in nmk_gpio_disable_lazy_irq()
619 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_get_mode() local
622 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; in nmk_gpio_get_mode()
623 if (!nmk_chip) in nmk_gpio_get_mode()
628 clk_enable(nmk_chip->clk); in nmk_gpio_get_mode()
630 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; in nmk_gpio_get_mode()
631 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; in nmk_gpio_get_mode()
633 clk_disable(nmk_chip->clk); in nmk_gpio_get_mode()
649 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); in nmk_gpio_irq_ack() local
651 clk_enable(nmk_chip->clk); in nmk_gpio_irq_ack()
652 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); in nmk_gpio_irq_ack()
653 clk_disable(nmk_chip->clk); in nmk_gpio_irq_ack()
661 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_irq_modify() argument
674 rimscval = &nmk_chip->rimsc; in __nmk_gpio_irq_modify()
675 fimscval = &nmk_chip->fimsc; in __nmk_gpio_irq_modify()
679 rimscval = &nmk_chip->rwimsc; in __nmk_gpio_irq_modify()
680 fimscval = &nmk_chip->fwimsc; in __nmk_gpio_irq_modify()
684 if (nmk_chip->edge_rising & bitmask) { in __nmk_gpio_irq_modify()
689 writel(*rimscval, nmk_chip->addr + rimscreg); in __nmk_gpio_irq_modify()
691 if (nmk_chip->edge_falling & bitmask) { in __nmk_gpio_irq_modify()
696 writel(*fimscval, nmk_chip->addr + fimscreg); in __nmk_gpio_irq_modify()
700 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, in __nmk_gpio_set_wake() argument
708 if (nmk_chip->sleepmode && on) { in __nmk_gpio_set_wake()
709 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, in __nmk_gpio_set_wake()
713 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); in __nmk_gpio_set_wake()
718 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_irq_maskunmask() local
722 nmk_chip = irq_data_get_irq_chip_data(d); in nmk_gpio_irq_maskunmask()
724 if (!nmk_chip) in nmk_gpio_irq_maskunmask()
727 clk_enable(nmk_chip->clk); in nmk_gpio_irq_maskunmask()
729 spin_lock(&nmk_chip->lock); in nmk_gpio_irq_maskunmask()
731 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); in nmk_gpio_irq_maskunmask()
733 if (!(nmk_chip->real_wake & bitmask)) in nmk_gpio_irq_maskunmask()
734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); in nmk_gpio_irq_maskunmask()
736 spin_unlock(&nmk_chip->lock); in nmk_gpio_irq_maskunmask()
738 clk_disable(nmk_chip->clk); in nmk_gpio_irq_maskunmask()
755 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_irq_set_wake() local
759 nmk_chip = irq_data_get_irq_chip_data(d); in nmk_gpio_irq_set_wake()
760 if (!nmk_chip) in nmk_gpio_irq_set_wake()
764 clk_enable(nmk_chip->clk); in nmk_gpio_irq_set_wake()
766 spin_lock(&nmk_chip->lock); in nmk_gpio_irq_set_wake()
769 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); in nmk_gpio_irq_set_wake()
772 nmk_chip->real_wake |= bitmask; in nmk_gpio_irq_set_wake()
774 nmk_chip->real_wake &= ~bitmask; in nmk_gpio_irq_set_wake()
776 spin_unlock(&nmk_chip->lock); in nmk_gpio_irq_set_wake()
778 clk_disable(nmk_chip->clk); in nmk_gpio_irq_set_wake()
787 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_irq_set_type() local
791 nmk_chip = irq_data_get_irq_chip_data(d); in nmk_gpio_irq_set_type()
793 if (!nmk_chip) in nmk_gpio_irq_set_type()
800 clk_enable(nmk_chip->clk); in nmk_gpio_irq_set_type()
801 spin_lock_irqsave(&nmk_chip->lock, flags); in nmk_gpio_irq_set_type()
804 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); in nmk_gpio_irq_set_type()
807 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); in nmk_gpio_irq_set_type()
809 nmk_chip->edge_rising &= ~bitmask; in nmk_gpio_irq_set_type()
811 nmk_chip->edge_rising |= bitmask; in nmk_gpio_irq_set_type()
813 nmk_chip->edge_falling &= ~bitmask; in nmk_gpio_irq_set_type()
815 nmk_chip->edge_falling |= bitmask; in nmk_gpio_irq_set_type()
818 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); in nmk_gpio_irq_set_type()
821 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); in nmk_gpio_irq_set_type()
823 spin_unlock_irqrestore(&nmk_chip->lock, flags); in nmk_gpio_irq_set_type()
824 clk_disable(nmk_chip->clk); in nmk_gpio_irq_set_type()
831 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); in nmk_gpio_irq_startup() local
833 clk_enable(nmk_chip->clk); in nmk_gpio_irq_startup()
840 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); in nmk_gpio_irq_shutdown() local
843 clk_disable(nmk_chip->clk); in nmk_gpio_irq_shutdown()
866 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); in nmk_gpio_irq_handler() local
869 clk_enable(nmk_chip->clk); in nmk_gpio_irq_handler()
870 status = readl(nmk_chip->addr + NMK_GPIO_IS); in nmk_gpio_irq_handler()
871 clk_disable(nmk_chip->clk); in nmk_gpio_irq_handler()
879 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); in nmk_gpio_latent_irq_handler() local
880 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); in nmk_gpio_latent_irq_handler()
889 struct nmk_gpio_chip *nmk_chip = in nmk_gpio_make_input() local
892 clk_enable(nmk_chip->clk); in nmk_gpio_make_input()
894 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); in nmk_gpio_make_input()
896 clk_disable(nmk_chip->clk); in nmk_gpio_make_input()
903 struct nmk_gpio_chip *nmk_chip = in nmk_gpio_get_input() local
908 clk_enable(nmk_chip->clk); in nmk_gpio_get_input()
910 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; in nmk_gpio_get_input()
912 clk_disable(nmk_chip->clk); in nmk_gpio_get_input()
920 struct nmk_gpio_chip *nmk_chip = in nmk_gpio_set_output() local
923 clk_enable(nmk_chip->clk); in nmk_gpio_set_output()
925 __nmk_gpio_set_output(nmk_chip, offset, val); in nmk_gpio_set_output()
927 clk_disable(nmk_chip->clk); in nmk_gpio_set_output()
933 struct nmk_gpio_chip *nmk_chip = in nmk_gpio_make_output() local
936 clk_enable(nmk_chip->clk); in nmk_gpio_make_output()
938 __nmk_gpio_make_output(nmk_chip, offset, val); in nmk_gpio_make_output()
940 clk_disable(nmk_chip->clk); in nmk_gpio_make_output()
954 struct nmk_gpio_chip *nmk_chip = in nmk_gpio_dbg_show_one() local
977 clk_enable(nmk_chip->clk); in nmk_gpio_dbg_show_one()
978 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); in nmk_gpio_dbg_show_one()
979 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); in nmk_gpio_dbg_show_one()
980 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); in nmk_gpio_dbg_show_one()
1017 if (nmk_chip->edge_rising & bitmask) in nmk_gpio_dbg_show_one()
1019 else if (nmk_chip->edge_falling & bitmask) in nmk_gpio_dbg_show_one()
1030 clk_disable(nmk_chip->clk); in nmk_gpio_dbg_show_one()
1159 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_populate_chip() local
1178 nmk_chip = nmk_gpio_chips[id]; in nmk_gpio_populate_chip()
1179 if (nmk_chip) in nmk_gpio_populate_chip()
1180 return nmk_chip; in nmk_gpio_populate_chip()
1182 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); in nmk_gpio_populate_chip()
1183 if (!nmk_chip) in nmk_gpio_populate_chip()
1186 nmk_chip->bank = id; in nmk_gpio_populate_chip()
1187 chip = &nmk_chip->chip; in nmk_gpio_populate_chip()
1197 nmk_chip->addr = base; in nmk_gpio_populate_chip()
1203 nmk_chip->clk = clk; in nmk_gpio_populate_chip()
1205 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); in nmk_gpio_populate_chip()
1206 nmk_gpio_chips[id] = nmk_chip; in nmk_gpio_populate_chip()
1207 return nmk_chip; in nmk_gpio_populate_chip()
1213 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_probe() local
1221 nmk_chip = nmk_gpio_populate_chip(np, dev); in nmk_gpio_probe()
1222 if (IS_ERR(nmk_chip)) { in nmk_gpio_probe()
1224 return PTR_ERR(nmk_chip); in nmk_gpio_probe()
1233 dev->id = nmk_chip->bank; in nmk_gpio_probe()
1246 nmk_chip->parent_irq = irq; in nmk_gpio_probe()
1247 nmk_chip->latent_parent_irq = latent_irq; in nmk_gpio_probe()
1248 nmk_chip->sleepmode = supports_sleepmode; in nmk_gpio_probe()
1249 spin_lock_init(&nmk_chip->lock); in nmk_gpio_probe()
1251 chip = &nmk_chip->chip; in nmk_gpio_probe()
1262 irqchip = &nmk_chip->irqchip; in nmk_gpio_probe()
1276 clk_enable(nmk_chip->clk); in nmk_gpio_probe()
1277 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); in nmk_gpio_probe()
1278 clk_disable(nmk_chip->clk); in nmk_gpio_probe()
1285 platform_set_drvdata(dev, nmk_chip); in nmk_gpio_probe()
1299 gpiochip_remove(&nmk_chip->chip); in nmk_gpio_probe()
1305 nmk_chip->parent_irq, in nmk_gpio_probe()
1307 if (nmk_chip->latent_parent_irq > 0) in nmk_gpio_probe()
1310 nmk_chip->latent_parent_irq, in nmk_gpio_probe()
1313 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); in nmk_gpio_probe()
1722 struct nmk_gpio_chip *nmk_chip; in nmk_pmx_set() local
1725 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); in nmk_pmx_set()
1726 if (!nmk_chip) { in nmk_pmx_set()
1734 clk_enable(nmk_chip->clk); in nmk_pmx_set()
1743 nmk_gpio_disable_lazy_irq(nmk_chip, bit); in nmk_pmx_set()
1745 __nmk_gpio_set_mode_safe(nmk_chip, bit, in nmk_pmx_set()
1747 clk_disable(nmk_chip->clk); in nmk_pmx_set()
1779 struct nmk_gpio_chip *nmk_chip; in nmk_gpio_request_enable() local
1792 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); in nmk_gpio_request_enable()
1796 clk_enable(nmk_chip->clk); in nmk_gpio_request_enable()
1799 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); in nmk_gpio_request_enable()
1800 clk_disable(nmk_chip->clk); in nmk_gpio_request_enable()
1846 struct nmk_gpio_chip *nmk_chip; in nmk_pin_config_set() local
1852 nmk_chip = find_nmk_gpio_from_pin(pin); in nmk_pin_config_set()
1853 if (!nmk_chip) { in nmk_pin_config_set()
1893 dev_dbg(nmk_chip->chip.dev, in nmk_pin_config_set()
1902 dev_dbg(nmk_chip->chip.dev, in nmk_pin_config_set()
1909 clk_enable(nmk_chip->clk); in nmk_pin_config_set()
1913 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); in nmk_pin_config_set()
1915 __nmk_gpio_make_output(nmk_chip, bit, val); in nmk_pin_config_set()
1917 __nmk_gpio_make_input(nmk_chip, bit); in nmk_pin_config_set()
1918 __nmk_gpio_set_pull(nmk_chip, bit, pull); in nmk_pin_config_set()
1921 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); in nmk_pin_config_set()
1923 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); in nmk_pin_config_set()
1924 clk_disable(nmk_chip->clk); in nmk_pin_config_set()
2018 struct nmk_gpio_chip *nmk_chip; in nmk_pinctrl_probe() local
2025 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); in nmk_pinctrl_probe()
2026 if (IS_ERR(nmk_chip)) in nmk_pinctrl_probe()