Lines Matching refs:smu_registers

202 	writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);  in sci_controller_isr()
212 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
213 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
235 readl(&ihost->smu_registers->interrupt_status); in sci_controller_error_isr()
251 writel(0xff, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
252 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
570 &ihost->smu_registers->completion_queue_get); in sci_controller_process_completions()
586 readl(&ihost->smu_registers->interrupt_status); in sci_controller_error_handler()
592 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); in sci_controller_error_handler()
605 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_handler()
614 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in isci_intx_isr()
707 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_enable_interrupts()
713 writel(0xffffffff, &ihost->smu_registers->interrupt_mask); in sci_controller_disable_interrupts()
714 readl(&ihost->smu_registers->interrupt_mask); /* flush */ in sci_controller_disable_interrupts()
740 readl(&ihost->smu_registers->task_context_assignment[0]); in sci_controller_assign_task_entries()
747 &ihost->smu_registers->task_context_assignment[0]); in sci_controller_assign_task_entries()
765 &ihost->smu_registers->completion_queue_control); in sci_controller_initialize_completion_queue()
777 &ihost->smu_registers->completion_queue_get); in sci_controller_initialize_completion_queue()
786 &ihost->smu_registers->completion_queue_put); in sci_controller_initialize_completion_queue()
1074 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in sci_controller_completion_handler()
1076 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_completion_handler()
1077 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_completion_handler()
1137 &ihost->smu_registers->interrupt_coalesce_control); in isci_host_completion_routine()
1434 &ihost->smu_registers->interrupt_coalesce_control); in sci_controller_set_interrupt_coalescence()
1450 val = readl(&ihost->smu_registers->clock_gating_control); in sci_controller_ready_state_enter()
1455 writel(val, &ihost->smu_registers->clock_gating_control); in sci_controller_ready_state_enter()
1548 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control); in sci_controller_reset_hardware()
1554 writel(0x00000000, &ihost->smu_registers->completion_queue_get); in sci_controller_reset_hardware()
1560 writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status); in sci_controller_reset_hardware()
1631 ihost->smu_registers = smu_base; in sci_controller_construct()
2165 writel(0, &ihost->smu_registers->soft_reset_control); in sci_controller_initialize()
2175 status = readl(&ihost->smu_registers->control_status); in sci_controller_initialize()
2186 val = readl(&ihost->smu_registers->device_context_capacity); in sci_controller_initialize()
2305 writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower); in sci_controller_mem_init()
2306 writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper); in sci_controller_mem_init()
2308 writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower); in sci_controller_mem_init()
2309 writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper); in sci_controller_mem_init()
2311 writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower); in sci_controller_mem_init()
2312 writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper); in sci_controller_mem_init()
2457 writel(request, &ihost->smu_registers->post_context_port); in sci_controller_post_request()