Lines Matching refs:uint32_t
244 uint32_t test_mask;
245 uint32_t test_value;
250 uint32_t test_mask;
251 uint32_t xor_value;
252 uint32_t or_value;
261 uint32_t arg1;
262 uint32_t arg2;
267 uint32_t dr_addr;
268 uint32_t dr_value;
269 uint32_t ar_addr;
270 uint32_t ar_value;
277 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
291 uint32_t entry_type;
292 uint32_t entry_size;
293 uint32_t entry_capture_size;
305 uint32_t addr;
311 uint32_t data_size;
312 uint32_t op_count;
321 uint32_t value_1;
322 uint32_t value_2;
323 uint32_t value_3;
328 uint32_t tag_reg_addr;
333 uint32_t data_size;
334 uint32_t op_count;
335 uint32_t control_addr;
341 uint32_t read_addr;
352 uint32_t rsvd_0;
353 uint32_t rsvd_1;
354 uint32_t data_size;
355 uint32_t op_count;
356 uint32_t rsvd_2;
357 uint32_t rsvd_3;
358 uint32_t read_addr;
359 uint32_t read_addr_stride;
365 uint32_t rsvd[6];
366 uint32_t read_addr;
367 uint32_t read_data_size;
373 uint32_t desc_card_addr;
376 uint32_t start_dma_cmd;
378 uint32_t read_addr;
379 uint32_t read_data_size;
385 uint32_t rsvd[6];
386 uint32_t read_addr;
387 uint32_t read_data_size;
393 uint32_t select_addr;
394 uint32_t rsvd_0;
395 uint32_t data_size;
396 uint32_t op_count;
397 uint32_t select_value;
398 uint32_t select_value_stride;
399 uint32_t read_addr;
400 uint32_t rsvd_1;
406 uint32_t select_addr;
411 uint32_t data_size;
412 uint32_t op_count;
413 uint32_t rsvd_1;
414 uint32_t rsvd_2;
415 uint32_t read_addr;
426 uint32_t select_addr;
427 uint32_t read_addr;
428 uint32_t select_value;
431 uint32_t poll_wait;
432 uint32_t poll_mask;
433 uint32_t data_size;
434 uint32_t rsvd_1;
439 uint32_t addr_1;
440 uint32_t value;
444 uint32_t poll;
445 uint32_t mask;
446 uint32_t modify_mask;
447 uint32_t data_size;
448 uint32_t rsvd;
455 uint32_t addr_1;
456 uint32_t addr_2;
457 uint32_t value_1;
461 uint32_t poll;
462 uint32_t mask;
463 uint32_t value_2;
464 uint32_t data_size;
470 uint32_t addr_1;
471 uint32_t addr_2;
472 uint32_t value_1;
473 uint32_t value_2;
474 uint32_t poll;
475 uint32_t mask;
476 uint32_t data_size;
477 uint32_t rsvd;
484 uint32_t select_addr_1;
485 uint32_t select_addr_2;
486 uint32_t select_value_1;
487 uint32_t select_value_2;
488 uint32_t op_count;
489 uint32_t select_value_mask;
490 uint32_t read_addr;
499 uint32_t addr_1;
500 uint32_t addr_2;
501 uint32_t value_1;
502 uint32_t value_2;
503 uint32_t poll_wait;
504 uint32_t poll_mask;
505 uint32_t modify_mask;
506 uint32_t data_size;
511 uint32_t request_desc; /* IDC request descriptor */
512 uint32_t info1; /* IDC additional info */
513 uint32_t info2; /* IDC additional info */
514 uint32_t info3; /* IDC additional info */
538 static const uint32_t qla8044_reg_tbl[] = {
571 uint32_t entry_type;
572 uint32_t first_entry_offset;
573 uint32_t size_of_template;
574 uint32_t capture_debug_level;
575 uint32_t num_of_entries;
576 uint32_t version;
577 uint32_t driver_timestamp;
578 uint32_t checksum;
580 uint32_t driver_capture_mask;
581 uint32_t driver_info_word2;
582 uint32_t driver_info_word3;
583 uint32_t driver_info_word4;
585 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
586 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
587 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
592 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */