Lines Matching refs:uint32_t

264 	uint32_t mbox_cmd;
266 	uint32_t pid;
273         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
290 	uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
296 	int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
297 			  struct ddb_entry *ddb_entry, uint32_t state);
311 	uint32_t default_time2wait;	  /* Default Min time between
367 			uint32_t data_size;
371 			uint32_t status;
372 			uint32_t pid;
373 			uint32_t data_size;
381 	uint32_t flash_conf_off;
382 	uint32_t flash_data_off;
384 	uint32_t fdt_wrt_disable;
385 	uint32_t fdt_erase_cmd;
386 	uint32_t fdt_block_size;
387 	uint32_t fdt_unprotect_sec_cmd;
388 	uint32_t fdt_protect_sec_cmd;
390 	uint32_t flt_region_flt;
391 	uint32_t flt_region_fdt;
392 	uint32_t flt_region_boot;
393 	uint32_t flt_region_bootload;
394 	uint32_t flt_region_fw;
396 	uint32_t flt_iscsi_param;
397 	uint32_t flt_region_chap;
398 	uint32_t flt_chap_size;
399 	uint32_t flt_region_ddb;
400 	uint32_t flt_ddb_size;
404 	uint32_t int_vec_bit;
405 	uint32_t tgt_status_reg;
406 	uint32_t tgt_mask_reg;
407 	uint32_t pci_int_reg;
436 	void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
445 	uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
446 	void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
447 	int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
448 	int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
452 	void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
457 	uint32_t size;
458 	uint32_t size_cmask_02;
459 	uint32_t size_cmask_04;
460 	uint32_t size_cmask_08;
461 	uint32_t size_cmask_10;
462 	uint32_t size_cmask_FF;
463 	uint32_t version;
475 	uint32_t ipv6_options;
476 	uint32_t ipv6_addl_options;
504 	uint32_t ipv6_nd_reach_time;
505 	uint32_t ipv6_nd_rexmit_timer;
506 	uint32_t ipv6_nd_stale_timeout;
508 	uint32_t ipv6_gw_advrt_mtu;
608 	uint32_t tot_ddbs;
632 	uint32_t eeprom_cmd_data;
642 	uint32_t bytes_xfered;
643 	uint32_t spurious_int_count;
644 	uint32_t aborted_io_count;
645 	uint32_t io_timeout_count;
646 	uint32_t mailbox_timeout_count;
647 	uint32_t seconds_since_last_intr;
648 	uint32_t seconds_since_last_heartbeat;
649 	uint32_t mac_index;
653 	uint32_t firmware_version[2];
654 	uint32_t patch_number;
655 	uint32_t build_number;
656 	uint32_t board_id;
670 	uint32_t firmware_state;
671 	uint32_t addl_fw_state;
679 	uint32_t timer_active;
683 	uint32_t retry_reset_ha_cnt;
684 	uint32_t isp_reset_timer;	/* reset test timer */
685 	uint32_t nic_reset_timer;	/* simulated nic reset test timer */
728 	volatile uint32_t mbox_status[MBOX_REG_COUNT];
746 	uint32_t crb_win;
747 	uint32_t curr_window;
748 	uint32_t ddr_mn_window;
760 	uint32_t fw_heartbeat_counter;
767 	uint32_t nx_dev_init_timeout;
768 	uint32_t nx_reset_timeout;
770 	uint32_t fw_dump_size;
771 	uint32_t fw_dump_capture_mask;
773 	uint32_t fw_dump_tmplt_size;
774 	uint32_t fw_dump_skip_size;
785 	uint32_t fw_uptime_secs;  /* seconds elapsed since fw bootup */
786 	uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
789 	uint32_t flash_state;
822 	uint32_t mrb_index;
824 	uint32_t *reg_tbl;
829 	uint32_t pf_bit;
845 	uint32_t req_len;
848 	uint32_t resp_len;
1062 				      const uint32_t crb_reg)  in qla4_8xxx_rd_direct()
1068 				       const uint32_t crb_reg,  in qla4_8xxx_wr_direct()
1069 				       const uint32_t value)  in qla4_8xxx_wr_direct()