124 	u32 reg_val;  in mtk_spi_reset()  local
127 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
128 	reg_val |= SPI_CMD_RST;  in mtk_spi_reset()
129 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
131 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
132 	reg_val &= ~SPI_CMD_RST;  in mtk_spi_reset()
133 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
140 	u32 reg_val;  in mtk_spi_prepare_message()  local
148 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
150 		reg_val |= SPI_CMD_CPHA;  in mtk_spi_prepare_message()
152 		reg_val &= ~SPI_CMD_CPHA;  in mtk_spi_prepare_message()
154 		reg_val |= SPI_CMD_CPOL;  in mtk_spi_prepare_message()
156 		reg_val &= ~SPI_CMD_CPOL;  in mtk_spi_prepare_message()
157 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
159 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
163 		reg_val |= SPI_CMD_TXMSBF;  in mtk_spi_prepare_message()
165 		reg_val &= ~SPI_CMD_TXMSBF;  in mtk_spi_prepare_message()
167 		reg_val |= SPI_CMD_RXMSBF;  in mtk_spi_prepare_message()
169 		reg_val &= ~SPI_CMD_RXMSBF;  in mtk_spi_prepare_message()
173 	reg_val &= ~SPI_CMD_TX_ENDIAN;  in mtk_spi_prepare_message()
174 	reg_val &= ~SPI_CMD_RX_ENDIAN;  in mtk_spi_prepare_message()
176 	reg_val |= SPI_CMD_TX_ENDIAN;  in mtk_spi_prepare_message()
177 	reg_val |= SPI_CMD_RX_ENDIAN;  in mtk_spi_prepare_message()
181 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;  in mtk_spi_prepare_message()
184 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);  in mtk_spi_prepare_message()
187 	reg_val &= ~SPI_CMD_DEASSERT;  in mtk_spi_prepare_message()
189 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
201 	u32 reg_val;  in mtk_spi_set_cs()  local
204 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
206 		reg_val |= SPI_CMD_PAUSE_EN;  in mtk_spi_set_cs()
207 		writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
209 		reg_val &= ~SPI_CMD_PAUSE_EN;  in mtk_spi_set_cs()
210 		writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
219 	u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;  in mtk_spi_prepare_transfer()  local
231 	reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);  in mtk_spi_prepare_transfer()
232 	reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);  in mtk_spi_prepare_transfer()
233 	reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);  in mtk_spi_prepare_transfer()
234 	reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);  in mtk_spi_prepare_transfer()
235 	writel(reg_val, mdata->base + SPI_CFG0_REG);  in mtk_spi_prepare_transfer()
237 	reg_val = readl(mdata->base + SPI_CFG1_REG);  in mtk_spi_prepare_transfer()
238 	reg_val &= ~SPI_CFG1_CS_IDLE_MASK;  in mtk_spi_prepare_transfer()
239 	reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);  in mtk_spi_prepare_transfer()
240 	writel(reg_val, mdata->base + SPI_CFG1_REG);  in mtk_spi_prepare_transfer()
245 	u32 packet_size, packet_loop, reg_val;  in mtk_spi_setup_packet()  local
251 	reg_val = readl(mdata->base + SPI_CFG1_REG);  in mtk_spi_setup_packet()
252 	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);  in mtk_spi_setup_packet()
253 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;  in mtk_spi_setup_packet()
254 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;  in mtk_spi_setup_packet()
255 	writel(reg_val, mdata->base + SPI_CFG1_REG);  in mtk_spi_setup_packet()
421 	u32 cmd, reg_val, cnt;  in mtk_spi_interrupt()  local
426 	reg_val = readl(mdata->base + SPI_STATUS0_REG);  in mtk_spi_interrupt()
427 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)  in mtk_spi_interrupt()