Lines Matching refs:tspi
219 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi, in tegra_spi_readl() argument
222 return readl(tspi->base + reg); in tegra_spi_readl()
225 static inline void tegra_spi_writel(struct tegra_spi_data *tspi, in tegra_spi_writel() argument
228 writel(val, tspi->base + reg); in tegra_spi_writel()
232 readl(tspi->base + SPI_COMMAND1); in tegra_spi_writel()
235 static void tegra_spi_clear_status(struct tegra_spi_data *tspi) in tegra_spi_clear_status() argument
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS); in tegra_spi_clear_status()
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS); in tegra_spi_clear_status()
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_clear_status()
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR, in tegra_spi_clear_status()
251 struct spi_device *spi, struct tegra_spi_data *tspi, in tegra_spi_calculate_curr_xfer_param() argument
254 unsigned remain_len = t->len - tspi->cur_pos; in tegra_spi_calculate_curr_xfer_param()
260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_spi_calculate_curr_xfer_param()
263 tspi->is_packed = 1; in tegra_spi_calculate_curr_xfer_param()
264 tspi->words_per_32bit = 32/bits_per_word; in tegra_spi_calculate_curr_xfer_param()
266 tspi->is_packed = 0; in tegra_spi_calculate_curr_xfer_param()
267 tspi->words_per_32bit = 1; in tegra_spi_calculate_curr_xfer_param()
270 if (tspi->is_packed) { in tegra_spi_calculate_curr_xfer_param()
271 max_len = min(remain_len, tspi->max_buf_size); in tegra_spi_calculate_curr_xfer_param()
272 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_spi_calculate_curr_xfer_param()
275 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_spi_calculate_curr_xfer_param()
276 max_word = min(max_word, tspi->max_buf_size/4); in tegra_spi_calculate_curr_xfer_param()
277 tspi->curr_dma_words = max_word; in tegra_spi_calculate_curr_xfer_param()
284 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_fill_tx_fifo_from_client_txbuf() argument
293 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
295 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_fill_tx_fifo_from_client_txbuf()
298 if (tspi->is_packed) { in tegra_spi_fill_tx_fifo_from_client_txbuf()
299 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_spi_fill_tx_fifo_from_client_txbuf()
300 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_spi_fill_tx_fifo_from_client_txbuf()
301 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
308 tegra_spi_writel(tspi, x, SPI_TX_FIFO); in tegra_spi_fill_tx_fifo_from_client_txbuf()
311 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_spi_fill_tx_fifo_from_client_txbuf()
313 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
317 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_spi_fill_tx_fifo_from_client_txbuf()
320 tegra_spi_writel(tspi, x, SPI_TX_FIFO); in tegra_spi_fill_tx_fifo_from_client_txbuf()
323 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
328 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_read_rx_fifo_to_client_rxbuf() argument
335 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
337 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_read_rx_fifo_to_client_rxbuf()
339 if (tspi->is_packed) { in tegra_spi_read_rx_fifo_to_client_rxbuf()
340 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
342 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO); in tegra_spi_read_rx_fifo_to_client_rxbuf()
347 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
348 read_words += tspi->curr_dma_words; in tegra_spi_read_rx_fifo_to_client_rxbuf()
353 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; in tegra_spi_read_rx_fifo_to_client_rxbuf()
355 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_spi_read_rx_fifo_to_client_rxbuf()
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
365 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_copy_client_txbuf_to_spi_txbuf() argument
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
369 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
371 if (tspi->is_packed) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
374 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
378 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
379 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
381 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
384 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
387 tspi->tx_dma_buf[count] = x; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
390 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
393 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
394 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
398 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf() argument
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
402 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
404 if (tspi->is_packed) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
405 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
407 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
411 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
414 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
415 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
417 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
421 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
424 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
425 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
435 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len) in tegra_spi_start_tx_dma() argument
437 reinit_completion(&tspi->tx_dma_complete); in tegra_spi_start_tx_dma()
438 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_spi_start_tx_dma()
439 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_spi_start_tx_dma()
441 if (!tspi->tx_dma_desc) { in tegra_spi_start_tx_dma()
442 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_spi_start_tx_dma()
446 tspi->tx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_tx_dma()
447 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_spi_start_tx_dma()
449 dmaengine_submit(tspi->tx_dma_desc); in tegra_spi_start_tx_dma()
450 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_spi_start_tx_dma()
454 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len) in tegra_spi_start_rx_dma() argument
456 reinit_completion(&tspi->rx_dma_complete); in tegra_spi_start_rx_dma()
457 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_spi_start_rx_dma()
458 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_spi_start_rx_dma()
460 if (!tspi->rx_dma_desc) { in tegra_spi_start_rx_dma()
461 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_spi_start_rx_dma()
465 tspi->rx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_rx_dma()
466 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_spi_start_rx_dma()
468 dmaengine_submit(tspi->rx_dma_desc); in tegra_spi_start_rx_dma()
469 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_spi_start_rx_dma()
474 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_start_dma_based_transfer() argument
482 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_start_dma_based_transfer()
484 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", in tegra_spi_start_dma_based_transfer()
489 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); in tegra_spi_start_dma_based_transfer()
490 tegra_spi_writel(tspi, val, SPI_DMA_BLK); in tegra_spi_start_dma_based_transfer()
492 if (tspi->is_packed) in tegra_spi_start_dma_based_transfer()
493 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_spi_start_dma_based_transfer()
496 len = tspi->curr_dma_words * 4; in tegra_spi_start_dma_based_transfer()
506 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
509 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_dma_based_transfer()
512 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_dma_based_transfer()
513 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
515 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_spi_start_dma_based_transfer()
516 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t); in tegra_spi_start_dma_based_transfer()
517 ret = tegra_spi_start_tx_dma(tspi, len); in tegra_spi_start_dma_based_transfer()
519 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
525 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_spi_start_dma_based_transfer()
527 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_start_dma_based_transfer()
528 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_start_dma_based_transfer()
530 ret = tegra_spi_start_rx_dma(tspi, len); in tegra_spi_start_dma_based_transfer()
532 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
534 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
535 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_start_dma_based_transfer()
539 tspi->is_curr_dma_xfer = true; in tegra_spi_start_dma_based_transfer()
540 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
543 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_dma_based_transfer()
548 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_start_cpu_based_transfer() argument
553 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
554 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t); in tegra_spi_start_cpu_based_transfer()
556 cur_words = tspi->curr_dma_words; in tegra_spi_start_cpu_based_transfer()
559 tegra_spi_writel(tspi, val, SPI_DMA_BLK); in tegra_spi_start_cpu_based_transfer()
562 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
565 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_cpu_based_transfer()
568 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_cpu_based_transfer()
569 tspi->dma_control_reg = val; in tegra_spi_start_cpu_based_transfer()
571 tspi->is_curr_dma_xfer = false; in tegra_spi_start_cpu_based_transfer()
574 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_cpu_based_transfer()
578 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, in tegra_spi_init_dma_param() argument
587 dma_chan = dma_request_slave_channel_reason(tspi->dev, in tegra_spi_init_dma_param()
592 dev_err(tspi->dev, in tegra_spi_init_dma_param()
597 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_spi_init_dma_param()
600 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_spi_init_dma_param()
606 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; in tegra_spi_init_dma_param()
610 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; in tegra_spi_init_dma_param()
619 tspi->rx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
620 tspi->rx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
621 tspi->rx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
623 tspi->tx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
624 tspi->tx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
625 tspi->tx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
630 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_spi_init_dma_param()
635 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, in tegra_spi_deinit_dma_param() argument
643 dma_buf = tspi->rx_dma_buf; in tegra_spi_deinit_dma_param()
644 dma_chan = tspi->rx_dma_chan; in tegra_spi_deinit_dma_param()
645 dma_phys = tspi->rx_dma_phys; in tegra_spi_deinit_dma_param()
646 tspi->rx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
647 tspi->rx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
649 dma_buf = tspi->tx_dma_buf; in tegra_spi_deinit_dma_param()
650 dma_chan = tspi->tx_dma_chan; in tegra_spi_deinit_dma_param()
651 dma_phys = tspi->tx_dma_phys; in tegra_spi_deinit_dma_param()
652 tspi->tx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
653 tspi->tx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
658 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_spi_deinit_dma_param()
665 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup_transfer_one() local
671 if (speed != tspi->cur_speed) { in tegra_spi_setup_transfer_one()
672 clk_set_rate(tspi->clk, speed); in tegra_spi_setup_transfer_one()
673 tspi->cur_speed = speed; in tegra_spi_setup_transfer_one()
676 tspi->cur_spi = spi; in tegra_spi_setup_transfer_one()
677 tspi->cur_pos = 0; in tegra_spi_setup_transfer_one()
678 tspi->cur_rx_pos = 0; in tegra_spi_setup_transfer_one()
679 tspi->cur_tx_pos = 0; in tegra_spi_setup_transfer_one()
680 tspi->curr_xfer = t; in tegra_spi_setup_transfer_one()
683 tegra_spi_clear_status(tspi); in tegra_spi_setup_transfer_one()
685 command1 = tspi->def_command1_reg; in tegra_spi_setup_transfer_one()
699 if (tspi->cs_control) { in tegra_spi_setup_transfer_one()
700 if (tspi->cs_control != spi) in tegra_spi_setup_transfer_one()
701 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_setup_transfer_one()
702 tspi->cs_control = NULL; in tegra_spi_setup_transfer_one()
704 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_setup_transfer_one()
712 tegra_spi_writel(tspi, 0, SPI_COMMAND2); in tegra_spi_setup_transfer_one()
714 command1 = tspi->command1_reg; in tegra_spi_setup_transfer_one()
725 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_start_transfer_one() local
729 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t); in tegra_spi_start_transfer_one()
731 if (tspi->is_packed) in tegra_spi_start_transfer_one()
735 tspi->cur_direction = 0; in tegra_spi_start_transfer_one()
738 tspi->cur_direction |= DATA_DIR_RX; in tegra_spi_start_transfer_one()
742 tspi->cur_direction |= DATA_DIR_TX; in tegra_spi_start_transfer_one()
745 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_start_transfer_one()
746 tspi->command1_reg = command1; in tegra_spi_start_transfer_one()
748 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", in tegra_spi_start_transfer_one()
749 tspi->def_command1_reg, (unsigned)command1); in tegra_spi_start_transfer_one()
752 ret = tegra_spi_start_dma_based_transfer(tspi, t); in tegra_spi_start_transfer_one()
754 ret = tegra_spi_start_cpu_based_transfer(tspi, t); in tegra_spi_start_transfer_one()
760 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup() local
771 ret = pm_runtime_get_sync(tspi->dev); in tegra_spi_setup()
773 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_spi_setup()
777 spin_lock_irqsave(&tspi->lock, flags); in tegra_spi_setup()
778 val = tspi->def_command1_reg; in tegra_spi_setup()
783 tspi->def_command1_reg = val; in tegra_spi_setup()
784 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_setup()
785 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_spi_setup()
787 pm_runtime_put(tspi->dev); in tegra_spi_setup()
806 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_transfer_one_message() local
818 reinit_completion(&tspi->xfer_completion); in tegra_spi_transfer_one_message()
830 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
836 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_spi_transfer_one_message()
839 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
845 if (tspi->tx_status || tspi->rx_status) { in tegra_spi_transfer_one_message()
846 dev_err(tspi->dev, "Error in Transfer\n"); in tegra_spi_transfer_one_message()
854 tegra_spi_writel(tspi, tspi->def_command1_reg, in tegra_spi_transfer_one_message()
861 tspi->cs_control = spi; in tegra_spi_transfer_one_message()
863 tegra_spi_writel(tspi, tspi->def_command1_reg, in tegra_spi_transfer_one_message()
868 tegra_spi_writel(tspi, tspi->def_command1_reg, in tegra_spi_transfer_one_message()
881 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) in handle_cpu_based_xfer() argument
883 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
886 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
887 if (tspi->tx_status || tspi->rx_status) { in handle_cpu_based_xfer()
888 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n", in handle_cpu_based_xfer()
889 tspi->status_reg); in handle_cpu_based_xfer()
890 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", in handle_cpu_based_xfer()
891 tspi->command1_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
892 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
894 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
895 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
899 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
900 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t); in handle_cpu_based_xfer()
902 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
903 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
905 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
907 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
908 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
912 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
913 tegra_spi_start_cpu_based_transfer(tspi, t); in handle_cpu_based_xfer()
915 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
919 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) in handle_dma_based_xfer() argument
921 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
928 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
929 if (tspi->tx_status) { in handle_dma_based_xfer()
930 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
934 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
936 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
937 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
943 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
944 if (tspi->rx_status) { in handle_dma_based_xfer()
945 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
949 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
951 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
952 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
958 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
960 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n", in handle_dma_based_xfer()
961 tspi->status_reg); in handle_dma_based_xfer()
962 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", in handle_dma_based_xfer()
963 tspi->command1_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
964 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
966 reset_control_deassert(tspi->rst); in handle_dma_based_xfer()
967 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
968 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
972 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
973 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t); in handle_dma_based_xfer()
975 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
976 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
978 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
980 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
981 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
986 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
987 tspi, t); in handle_dma_based_xfer()
989 err = tegra_spi_start_dma_based_transfer(tspi, t); in handle_dma_based_xfer()
991 err = tegra_spi_start_cpu_based_transfer(tspi, t); in handle_dma_based_xfer()
994 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1000 struct tegra_spi_data *tspi = context_data; in tegra_spi_isr_thread() local
1002 if (!tspi->is_curr_dma_xfer) in tegra_spi_isr_thread()
1003 return handle_cpu_based_xfer(tspi); in tegra_spi_isr_thread()
1004 return handle_dma_based_xfer(tspi); in tegra_spi_isr_thread()
1009 struct tegra_spi_data *tspi = context_data; in tegra_spi_isr() local
1011 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_isr()
1012 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_isr()
1013 tspi->tx_status = tspi->status_reg & in tegra_spi_isr()
1016 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_isr()
1017 tspi->rx_status = tspi->status_reg & in tegra_spi_isr()
1019 tegra_spi_clear_status(tspi); in tegra_spi_isr()
1033 struct tegra_spi_data *tspi; in tegra_spi_probe() local
1037 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); in tegra_spi_probe()
1043 tspi = spi_master_get_devdata(master); in tegra_spi_probe()
1056 tspi->master = master; in tegra_spi_probe()
1057 tspi->dev = &pdev->dev; in tegra_spi_probe()
1058 spin_lock_init(&tspi->lock); in tegra_spi_probe()
1061 tspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_spi_probe()
1062 if (IS_ERR(tspi->base)) { in tegra_spi_probe()
1063 ret = PTR_ERR(tspi->base); in tegra_spi_probe()
1066 tspi->phys = r->start; in tegra_spi_probe()
1069 tspi->irq = spi_irq; in tegra_spi_probe()
1070 ret = request_threaded_irq(tspi->irq, tegra_spi_isr, in tegra_spi_probe()
1072 dev_name(&pdev->dev), tspi); in tegra_spi_probe()
1075 tspi->irq); in tegra_spi_probe()
1079 tspi->clk = devm_clk_get(&pdev->dev, "spi"); in tegra_spi_probe()
1080 if (IS_ERR(tspi->clk)) { in tegra_spi_probe()
1082 ret = PTR_ERR(tspi->clk); in tegra_spi_probe()
1086 tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); in tegra_spi_probe()
1087 if (IS_ERR(tspi->rst)) { in tegra_spi_probe()
1089 ret = PTR_ERR(tspi->rst); in tegra_spi_probe()
1093 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; in tegra_spi_probe()
1094 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_spi_probe()
1096 ret = tegra_spi_init_dma_param(tspi, true); in tegra_spi_probe()
1099 ret = tegra_spi_init_dma_param(tspi, false); in tegra_spi_probe()
1102 tspi->max_buf_size = tspi->dma_buf_size; in tegra_spi_probe()
1103 init_completion(&tspi->tx_dma_complete); in tegra_spi_probe()
1104 init_completion(&tspi->rx_dma_complete); in tegra_spi_probe()
1106 init_completion(&tspi->xfer_completion); in tegra_spi_probe()
1120 tspi->def_command1_reg = SPI_M_S; in tegra_spi_probe()
1121 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_probe()
1136 tegra_spi_deinit_dma_param(tspi, false); in tegra_spi_probe()
1138 tegra_spi_deinit_dma_param(tspi, true); in tegra_spi_probe()
1140 free_irq(spi_irq, tspi); in tegra_spi_probe()
1149 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_remove() local
1151 free_irq(tspi->irq, tspi); in tegra_spi_remove()
1153 if (tspi->tx_dma_chan) in tegra_spi_remove()
1154 tegra_spi_deinit_dma_param(tspi, false); in tegra_spi_remove()
1156 if (tspi->rx_dma_chan) in tegra_spi_remove()
1157 tegra_spi_deinit_dma_param(tspi, true); in tegra_spi_remove()
1177 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_resume() local
1185 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_resume()
1195 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_runtime_suspend() local
1198 tegra_spi_readl(tspi, SPI_COMMAND1); in tegra_spi_runtime_suspend()
1200 clk_disable_unprepare(tspi->clk); in tegra_spi_runtime_suspend()
1207 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_runtime_resume() local
1210 ret = clk_prepare_enable(tspi->clk); in tegra_spi_runtime_resume()
1212 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_spi_runtime_resume()