Lines Matching refs:sOutW
1889 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sPCIInitController()
2631 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sInitController()
2688 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ in sReadAiopNumChan()
2690 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ in sReadAiopNumChan()
2819 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sInitChan()
2820 sOutW(ChP->IndexData, 0); in sInitChan()
2826 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sInitChan()
2827 sOutW(ChP->IndexData, 0); in sInitChan()
2828 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sInitChan()
2829 sOutW(ChP->IndexData, 0); in sInitChan()
2831 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); in sInitChan()
2834 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); in sInitChan()
2905 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sFlushRxFIFO()
2906 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2907 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sFlushRxFIFO()
2908 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2947 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sFlushTxFIFO()
2948 sOutW(ChP->IndexData, 0); in sFlushTxFIFO()
2975 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ in sWriteTxPrioByte()