412 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))  macro
432 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
433 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
434 	out_be32(&FIFO_512x(port)->txalarm, 1);  in mpc512x_psc_fifo_init()
435 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_fifo_init()
437 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
438 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
439 	out_be32(&FIFO_512x(port)->rxalarm, 1);  in mpc512x_psc_fifo_init()
440 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_fifo_init()
442 	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
443 	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
448 	return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);  in mpc512x_psc_raw_rx_rdy()
453 	return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);  in mpc512x_psc_raw_tx_rdy()
458 	return in_be32(&FIFO_512x(port)->rxsr)  in mpc512x_psc_rx_rdy()
459 	    & in_be32(&FIFO_512x(port)->rximr)  in mpc512x_psc_rx_rdy()
465 	return in_be32(&FIFO_512x(port)->txsr)  in mpc512x_psc_tx_rdy()
466 	    & in_be32(&FIFO_512x(port)->tximr)  in mpc512x_psc_tx_rdy()
472 	return in_be32(&FIFO_512x(port)->txsr)  in mpc512x_psc_tx_empty()
480 	rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);  in mpc512x_psc_stop_rx()
482 	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);  in mpc512x_psc_stop_rx()
489 	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);  in mpc512x_psc_start_tx()
491 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_start_tx()
498 	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);  in mpc512x_psc_stop_tx()
500 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_stop_tx()
505 	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));  in mpc512x_psc_rx_clr_irq()
510 	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));  in mpc512x_psc_tx_clr_irq()
515 	out_8(&FIFO_512x(port)->txdata_8, c);  in mpc512x_psc_write_char()
520 	return in_8(&FIFO_512x(port)->rxdata_8);  in mpc512x_psc_read_char()
526 		in_be32(&FIFO_512x(port)->tximr) << 16 |  in mpc512x_psc_cw_disable_ints()
527 		in_be32(&FIFO_512x(port)->rximr);  in mpc512x_psc_cw_disable_ints()
528 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_cw_disable_ints()
529 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_cw_disable_ints()
534 	out_be32(&FIFO_512x(port)->tximr,  in mpc512x_psc_cw_restore_ints()
536 	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);  in mpc512x_psc_cw_restore_ints()