Lines Matching refs:BIT0
418 #define RXRDYE BIT0
430 #define BRKE BIT0
431 #define IDLD BIT0
2168 while((status = read_reg(info,CST0)) & BIT0) in isr_rxrdy()
2579 if (status & BIT0 << shift) in synclinkmp_interrupt()
2588 if (dmastatus & BIT0 << shift) in synclinkmp_interrupt()
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4032 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in enable_loopback()
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4417 RegValue |= BIT0; in async_mode()
4430 RegValue |= (BIT1 + BIT0); in async_mode()
4455 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in async_mode()
4632 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in hdlc_mode()
4634 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); in hdlc_mode()
4758 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> in get_signals()
4773 RegValue &= ~BIT0; in set_signals()
4775 RegValue |= BIT0; in set_signals()