99 	struct ci_hdrc				*ci;  member
253 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)  in ci_role()  argument
255 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);  in ci_role()
256 	return ci->roles[ci->role];  in ci_role()
259 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)  in ci_role_start()  argument
266 	if (!ci->roles[role])  in ci_role_start()
269 	ret = ci->roles[role]->start(ci);  in ci_role_start()
271 		ci->role = role;  in ci_role_start()
275 static inline void ci_role_stop(struct ci_hdrc *ci)  in ci_role_stop()  argument
277 	enum ci_role role = ci->role;  in ci_role_stop()
282 	ci->role = CI_ROLE_END;  in ci_role_stop()
284 	ci->roles[role]->stop(ci);  in ci_role_stop()
295 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)  in hw_read_id_reg()  argument
297 	return ioread32(ci->hw_bank.abs + offset) & mask;  in hw_read_id_reg()
307 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,  in hw_write_id_reg()  argument
311 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)  in hw_write_id_reg()
314 	iowrite32(data, ci->hw_bank.abs + offset);  in hw_write_id_reg()
325 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)  in hw_read()  argument
327 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
341 static inline void __hw_write(struct ci_hdrc *ci, u32 val,  in __hw_write()  argument
344 	if (ci->imx28_write_fix)  in __hw_write()
357 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_write()  argument
361 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
364 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);  in hw_write()
375 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_clear()  argument
378 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
380 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);  in hw_test_and_clear()
393 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_write()  argument
396 	u32 val = hw_read(ci, reg, ~0);  in hw_test_and_write()
398 	hw_write(ci, reg, mask, data);  in hw_test_and_write()
408 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)  in ci_otg_is_fsm_mode()  argument
411 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;  in ci_otg_is_fsm_mode()
413 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&  in ci_otg_is_fsm_mode()
414 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||  in ci_otg_is_fsm_mode()
421 u32 hw_read_intr_enable(struct ci_hdrc *ci);
423 u32 hw_read_intr_status(struct ci_hdrc *ci);
425 int hw_device_reset(struct ci_hdrc *ci);
427 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
429 u8 hw_port_test_get(struct ci_hdrc *ci);
431 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
434 void ci_platform_configure(struct ci_hdrc *ci);