Lines Matching refs:AMD_BIT
275 tmp = AMD_BIT(UDC_DEVINT_SVC) | in udc_mask_unused_interrupts()
276 AMD_BIT(UDC_DEVINT_ENUM) | in udc_mask_unused_interrupts()
277 AMD_BIT(UDC_DEVINT_US) | in udc_mask_unused_interrupts()
278 AMD_BIT(UDC_DEVINT_UR) | in udc_mask_unused_interrupts()
279 AMD_BIT(UDC_DEVINT_ES) | in udc_mask_unused_interrupts()
280 AMD_BIT(UDC_DEVINT_SI) | in udc_mask_unused_interrupts()
281 AMD_BIT(UDC_DEVINT_SOF)| in udc_mask_unused_interrupts()
282 AMD_BIT(UDC_DEVINT_SC); in udc_mask_unused_interrupts()
359 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) { in UDC_QUEUE_CNAK()
431 tmp |= AMD_BIT(UDC_EPCTL_F); in udc_ep_enable()
485 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_ep_enable()
510 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in ep_init()
516 tmp |= AMD_BIT(ep->num); in ep_init()
526 tmp |= AMD_BIT(UDC_EPSTS_IN); in ep_init()
531 tmp |= AMD_BIT(UDC_EPCTL_F); in ep_init()
666 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L); in udc_init_bna_dummy()
917 td->status |= AMD_BIT(UDC_DMA_IN_STS_L); in udc_create_dma_chain()
939 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L); in prep_dma()
1003 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in prep_dma()
1055 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) in udc_get_last_dma_desc()
1072 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) { in udc_get_ppbdu_rxbytes()
1098 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_set_rde()
1161 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE); in udc_queue()
1169 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1221 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1389 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_set_halt()
1411 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_set_halt()
1455 tmp |= AMD_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()
1534 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG); in udc_basic_init()
1536 tmp |= AMD_BIT(UDC_DEVCFG_SP); in udc_basic_init()
1538 tmp |= AMD_BIT(UDC_DEVCFG_RWKP); in udc_basic_init()
1632 reg |= AMD_BIT(UDC_EPCTL_SNAK); in udc_setup_endpoints()
1762 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_soft_reset()
1783 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_timer_function()
1787 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) { in udc_timer_function()
1826 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) { in udc_handle_halt_state()
1840 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_handle_halt_state()
1891 tmp |= AMD_BIT(UDC_EPCTL_F); in activate_control_endpoints()
1940 AMD_BIT(UDC_DMA_OUT_STS_L); in activate_control_endpoints()
1956 tmp |= AMD_BIT(UDC_DEVCTL_MODE) in activate_control_endpoints()
1957 | AMD_BIT(UDC_DEVCTL_RDE) in activate_control_endpoints()
1958 | AMD_BIT(UDC_DEVCTL_TDE); in activate_control_endpoints()
1960 tmp |= AMD_BIT(UDC_DEVCTL_BF); in activate_control_endpoints()
1962 tmp |= AMD_BIT(UDC_DEVCTL_DU); in activate_control_endpoints()
1968 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1975 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
2055 tmp |= AMD_BIT(UDC_DEVCTL_SD); in amd5536_udc_stop()
2074 reg |= AMD_BIT(UDC_EPCTL_CNAK); in udc_process_cnak_queue()
2085 reg |= AMD_BIT(UDC_EPCTL_CNAK); in udc_process_cnak_queue()
2137 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_out_isr()
2141 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2151 if (tmp & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_out_isr()
2155 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2324 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_data_out_isr()
2351 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_in_isr()
2364 if (epsts & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_in_isr()
2370 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_in_isr()
2376 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) { in udc_data_in_isr()
2408 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2420 if ((epsts & AMD_BIT(UDC_EPSTS_IN)) in udc_data_in_isr()
2421 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) { in udc_data_in_isr()
2471 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_data_in_isr()
2480 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2509 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts); in udc_control_out_isr()
2513 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_control_out_isr()
2515 writel(AMD_BIT(UDC_EPSTS_BNA), in udc_control_out_isr()
2535 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in udc_control_out_isr()
2621 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2628 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_out_isr()
2637 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2701 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_control_out_isr()
2721 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); in udc_control_in_isr()
2725 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) { in udc_control_in_isr()
2730 writel(AMD_BIT(UDC_EPSTS_TDC), in udc_control_in_isr()
2734 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) { in udc_control_in_isr()
2739 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2746 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_in_isr()
2767 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_control_in_isr()
2800 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2822 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) { in udc_dev_isr()
2871 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) { in udc_dev_isr()
2931 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) { in udc_dev_isr()
2959 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_dev_isr()
2972 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2987 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) { in udc_dev_isr()
2997 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) { in udc_dev_isr()
3018 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) { in udc_dev_isr()
3024 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) { in udc_dev_isr()
3027 tmp |= AMD_BIT(UDC_DEVINT_US); in udc_dev_isr()
3053 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0)) in udc_irq()
3055 if (reg & AMD_BIT(UDC_EPINT_IN_EP0)) in udc_irq()
3145 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_pci_remove()
3274 reg |= AMD_BIT(UDC_DEVCTL_SD); in udc_probe()