221 #define u132_write_pcimem(u132, member, data) \  macro
1541 	retval = u132_write_pcimem(u132, fminterval,  in u132_periodic_reinit()
1545 	return u132_write_pcimem(u132, periodicstart,  in u132_periodic_reinit()
1570 	retval = u132_write_pcimem(u132, intrdisable, OHCI_INTR_MIE);  in u132_init()
1641 	retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1654 			retval = u132_write_pcimem(u132,  in u132_run()
1667 	retval = u132_write_pcimem(u132, cmdstatus, OHCI_HCR);  in u132_run()
1686 		retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1693 	retval = u132_write_pcimem(u132, ed_controlhead, 0x00000000);  in u132_run()
1696 	retval = u132_write_pcimem(u132, ed_bulkhead, 0x11000000);  in u132_run()
1699 	retval = u132_write_pcimem(u132, hcca, 0x00000000);  in u132_run()
1721 	retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1724 	retval = u132_write_pcimem(u132, cmdstatus, OHCI_BLF);  in u132_run()
1734 	retval = u132_write_pcimem(u132, roothub.status, RH_HS_DRWE);  in u132_run()
1737 	retval = u132_write_pcimem(u132, intrstatus, mask);  in u132_run()
1740 	retval = u132_write_pcimem(u132, intrdisable,  in u132_run()
1753 		retval = u132_write_pcimem(u132, roothub.a, roothub_a);  in u132_run()
1758 		retval = u132_write_pcimem(u132, roothub.a, roothub_a);  in u132_run()
1762 	retval = u132_write_pcimem(u132, roothub.status, RH_HS_LPSC);  in u132_run()
1765 	retval = u132_write_pcimem(u132, roothub.b,  in u132_run()
2672 				retval = u132_write_pcimem(u132,  in u132_roothub_portreset()
2681 		retval = u132_write_pcimem(u132, roothub.portstatus[port_index],  in u132_roothub_portreset()
2705 			return u132_write_pcimem(u132,  in u132_roothub_setportfeature()
2708 			return u132_write_pcimem(u132,  in u132_roothub_setportfeature()
2761 		return u132_write_pcimem(u132, roothub.portstatus[port_index],  in u132_roothub_clearportfeature()