111 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,  in i740outreg_mask()  function
127 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);  in i740fb_ddc_setscl()
128 	i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);  in i740fb_ddc_setscl()
135 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);  in i740fb_ddc_setsda()
136 	i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);  in i740fb_ddc_setsda()
143 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);  in i740fb_ddc_getscl()
152 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);  in i740fb_ddc_getsda()
718 	i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);  in vga_protect()
727 	i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);  in vga_unprotect()
756 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,  in i740fb_set_par()
810 	i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,  in i740fb_set_par()
812 	i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);  in i740fb_set_par()
813 	i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);  in i740fb_set_par()
814 	i740outreg_mask(par, XRX, DISPLAY_CNTL,  in i740fb_set_par()
816 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);  in i740fb_set_par()
817 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);  in i740fb_set_par()
821 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,  in i740fb_set_par()
831 	i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);  in i740fb_set_par()
832 	i740outreg_mask(par, XRX, IO_CTNL,  in i740fb_set_par()