Lines Matching refs:io_register

357 struct io_register {  struct
370 	struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];  argument
376 	struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
382 	struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
388 	struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
394 	struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
400 	struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
406 	struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
412 	struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
418 	struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
424 	struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
435 	struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
440 	struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
451 	struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
456 	struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
461 	struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
466 	struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
479 	struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
484 	struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
515 	struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
520 	struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
525 	struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
530 	struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
535 	struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
540 	struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
545 	struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
550 	struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
646 	struct io_register *reg,