102 	val = ioread32(bridge->base + DGCS);  in ca91cx42_VERR_irqhandler()
119 	val = ioread32(bridge->base + DGCS);  in ca91cx42_LERR_irqhandler()
140 			vec = ioread32(bridge->base +  in ca91cx42_VIRQ_irqhandler()
162 	enable = ioread32(bridge->base + LINT_EN);  in ca91cx42_irqhandler()
163 	stat = ioread32(bridge->base + LINT_STAT);  in ca91cx42_irqhandler()
264 	tmp = ioread32(bridge->base + LINT_STAT);  in ca91cx42_iack_received()
286 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_irq_set()
317 	tmp = ioread32(bridge->base + VINT_EN);  in ca91cx42_irq_generate()
331 	tmp = ioread32(bridge->base + VINT_EN);  in ca91cx42_irq_generate()
411 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
464 	ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_get()
466 	*vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);  in ca91cx42_slave_get()
467 	vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);  in ca91cx42_slave_get()
468 	pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);  in ca91cx42_slave_get()
659 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
767 	ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in __ca91cx42_master_get()
769 	pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);  in __ca91cx42_master_get()
770 	vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);  in __ca91cx42_master_get()
771 	pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);  in __ca91cx42_master_get()
898 		*(u32 *)(buf + done) = ioread32(addr + done);  in ca91cx42_master_read()
1016 	result = ioread32(image->kern_base + offset);  in ca91cx42_master_rmw()
1182 	tmp = ioread32(bridge->base + DGCS);  in ca91cx42_dma_busy()
1232 	val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1251 		val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1264 	val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1270 		val = ioread32(bridge->base + DCTL);  in ca91cx42_dma_list_exec()
1384 	*lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);  in ca91cx42_lm_get()
1385 	lm_ctl = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_get()
1430 	lm_ctl = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_attach()
1448 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_lm_attach()
1476 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_lm_detach()
1489 		tmp = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_detach()
1507 		slot = ioread32(bridge->base + VCSR_BS);  in ca91cx42_slot_get()
1580 	tmp = ioread32(bridge->base + VCSR_CTL);  in ca91cx42_crcsr_init()
1596 	tmp = ioread32(bridge->base + VCSR_CTL);  in ca91cx42_crcsr_exit()
1666 	data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;  in ca91cx42_probe()
1803 	data = ioread32(ca91cx42_device->base + MISC_CTL);  in ca91cx42_probe()