191 	iowrite32(serviced, bridge->base + LINT_STAT);  in ca91cx42_irqhandler()
212 	iowrite32(0, bridge->base + VINT_EN);  in ca91cx42_irq_init()
215 	iowrite32(0, bridge->base + LINT_EN);  in ca91cx42_irq_init()
217 	iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);  in ca91cx42_irq_init()
228 	iowrite32(0, bridge->base + LINT_MAP0);  in ca91cx42_irq_init()
229 	iowrite32(0, bridge->base + LINT_MAP1);  in ca91cx42_irq_init()
230 	iowrite32(0, bridge->base + LINT_MAP2);  in ca91cx42_irq_init()
237 	iowrite32(tmp, bridge->base + LINT_EN);  in ca91cx42_irq_init()
248 	iowrite32(0, bridge->base + VINT_EN);  in ca91cx42_irq_exit()
251 	iowrite32(0, bridge->base + LINT_EN);  in ca91cx42_irq_exit()
253 	iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);  in ca91cx42_irq_exit()
293 	iowrite32(tmp, bridge->base + LINT_EN);  in ca91cx42_irq_set()
320 	iowrite32(statid << 24, bridge->base + STATID);  in ca91cx42_irq_generate()
324 	iowrite32(tmp, bridge->base + VINT_EN);  in ca91cx42_irq_generate()
333 	iowrite32(tmp, bridge->base + VINT_EN);  in ca91cx42_irq_generate()
413 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
416 	iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);  in ca91cx42_slave_set()
417 	iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);  in ca91cx42_slave_set()
418 	iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);  in ca91cx42_slave_set()
436 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
441 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
661 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
732 	iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);  in ca91cx42_master_set()
733 	iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);  in ca91cx42_master_set()
734 	iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);  in ca91cx42_master_set()
737 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
742 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
952 		iowrite32(*(u32 *)(buf + done), addr + done);  in ca91cx42_master_write()
1004 	iowrite32(0, bridge->base + SCYC_CTL);  in ca91cx42_master_rmw()
1007 	iowrite32(mask, bridge->base + SCYC_EN);  in ca91cx42_master_rmw()
1008 	iowrite32(compare, bridge->base + SCYC_CMP);  in ca91cx42_master_rmw()
1009 	iowrite32(swap, bridge->base + SCYC_SWP);  in ca91cx42_master_rmw()
1010 	iowrite32(pci_addr, bridge->base + SCYC_ADDR);  in ca91cx42_master_rmw()
1013 	iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);  in ca91cx42_master_rmw()
1019 	iowrite32(0, bridge->base + SCYC_CTL);  in ca91cx42_master_rmw()
1228 	iowrite32(0, bridge->base + DTBC);  in ca91cx42_dma_list_exec()
1229 	iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);  in ca91cx42_dma_list_exec()
1241 	iowrite32(val, bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1245 	iowrite32(val, bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1252 		iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1363 	iowrite32(lm_base, bridge->base + LM_BS);  in ca91cx42_lm_set()
1364 	iowrite32(lm_ctl, bridge->base + LM_CTL);  in ca91cx42_lm_set()
1450 	iowrite32(tmp, bridge->base + LINT_EN);  in ca91cx42_lm_attach()
1455 		iowrite32(lm_ctl, bridge->base + LM_CTL);  in ca91cx42_lm_attach()
1478 	iowrite32(tmp, bridge->base + LINT_EN);  in ca91cx42_lm_detach()
1480 	iowrite32(CA91CX42_LINT_LM[monitor],  in ca91cx42_lm_detach()
1491 		iowrite32(tmp, bridge->base + LM_CTL);  in ca91cx42_lm_detach()
1559 		iowrite32(geoid << 27, bridge->base + VCSR_BS);  in ca91cx42_crcsr_init()
1578 	iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);  in ca91cx42_crcsr_init()
1582 	iowrite32(tmp, bridge->base + VCSR_CTL);  in ca91cx42_crcsr_init()
1598 	iowrite32(tmp, bridge->base + VCSR_CTL);  in ca91cx42_crcsr_exit()
1601 	iowrite32(0, bridge->base + VCSR_TO);  in ca91cx42_crcsr_exit()
1888 	iowrite32(0, bridge->base + LINT_EN);  in ca91cx42_remove()
1891 	iowrite32(0x00800000, bridge->base + LSI0_CTL);  in ca91cx42_remove()
1892 	iowrite32(0x00800000, bridge->base + LSI1_CTL);  in ca91cx42_remove()
1893 	iowrite32(0x00800000, bridge->base + LSI2_CTL);  in ca91cx42_remove()
1894 	iowrite32(0x00800000, bridge->base + LSI3_CTL);  in ca91cx42_remove()
1895 	iowrite32(0x00800000, bridge->base + LSI4_CTL);  in ca91cx42_remove()
1896 	iowrite32(0x00800000, bridge->base + LSI5_CTL);  in ca91cx42_remove()
1897 	iowrite32(0x00800000, bridge->base + LSI6_CTL);  in ca91cx42_remove()
1898 	iowrite32(0x00800000, bridge->base + LSI7_CTL);  in ca91cx42_remove()
1899 	iowrite32(0x00F00000, bridge->base + VSI0_CTL);  in ca91cx42_remove()
1900 	iowrite32(0x00F00000, bridge->base + VSI1_CTL);  in ca91cx42_remove()
1901 	iowrite32(0x00F00000, bridge->base + VSI2_CTL);  in ca91cx42_remove()
1902 	iowrite32(0x00F00000, bridge->base + VSI3_CTL);  in ca91cx42_remove()
1903 	iowrite32(0x00F00000, bridge->base + VSI4_CTL);  in ca91cx42_remove()
1904 	iowrite32(0x00F00000, bridge->base + VSI5_CTL);  in ca91cx42_remove()
1905 	iowrite32(0x00F00000, bridge->base + VSI6_CTL);  in ca91cx42_remove()
1906 	iowrite32(0x00F00000, bridge->base + VSI7_CTL);  in ca91cx42_remove()