159 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_PERR_irqhandler()
198 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
301 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);  in tsi148_irqhandler()
365 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_init()
366 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_init()
377 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_exit()
378 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_exit()
381 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);  in tsi148_irq_exit()
418 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
422 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
431 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
435 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
459 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
463 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
548 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
552 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
554 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
556 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
558 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
560 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
562 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
607 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
613 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
914 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1016 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1018 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1020 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1022 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1024 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1026 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1030 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1036 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1401 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);  in tsi148_master_rmw()
1402 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);  in tsi148_master_rmw()
1403 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);  in tsi148_master_rmw()
1404 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);  in tsi148_master_rmw()
1405 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);  in tsi148_master_rmw()
1410 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1418 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1857 	iowrite32be(bus_addr_high, bridge->base +  in tsi148_dma_list_exec()
1859 	iowrite32be(bus_addr_low, bridge->base +  in tsi148_dma_list_exec()
1866 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +  in tsi148_dma_list_exec()
1873 		iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +  in tsi148_dma_list_exec()
1990 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_set()
1991 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_set()
1992 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_set()
2088 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2092 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2097 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2120 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2124 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2126 	iowrite32be(TSI148_LCSR_INTC_LMC[monitor],  in tsi148_lm_detach()
2137 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2219 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_init()
2220 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_init()
2231 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2240 		iowrite32be(crat | TSI148_LCSR_CRAT_EN,  in tsi148_crcsr_init()
2271 	iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,  in tsi148_crcsr_exit()
2275 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_exit()
2276 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_exit()
2536 	iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);  in tsi148_probe()
2610 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_remove()
2612 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_remove()
2619 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);  in tsi148_remove()
2624 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);  in tsi148_remove()
2629 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_remove()
2630 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);  in tsi148_remove()
2631 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);  in tsi148_remove()
2637 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);  in tsi148_remove()
2642 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);  in tsi148_remove()
2643 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);  in tsi148_remove()