Lines Matching refs:RT5677_PWR_ANLG2
148 {RT5677_PWR_ANLG2 , 0x0000},
413 case RT5677_PWR_ANLG2: in rt5677_readable_register()
721 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_dsp_vad()
2417 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2422 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2441 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2446 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2509 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2516 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2615 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2618 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2663 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2702 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2705 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
4494 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4509 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); in rt5677_set_bias_level()