39 static struct s3c_ac97_info s3c_ac97;  variable
57 	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;  in s3c_ac97_activate()
61 	reinit_completion(&s3c_ac97.done);  in s3c_ac97_activate()
63 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_activate()
65 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_activate()
69 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_activate()
72 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_activate()
74 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_activate()
76 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))  in s3c_ac97_activate()
86 	mutex_lock(&s3c_ac97.lock);  in s3c_ac97_read()
90 	reinit_completion(&s3c_ac97.done);  in s3c_ac97_read()
92 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_read()
94 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_read()
98 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_read()
100 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_read()
102 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))  in s3c_ac97_read()
105 	stat = readl(s3c_ac97.regs + S3C_AC97_STAT);  in s3c_ac97_read()
113 	mutex_unlock(&s3c_ac97.lock);  in s3c_ac97_read()
123 	mutex_lock(&s3c_ac97.lock);  in s3c_ac97_write()
127 	reinit_completion(&s3c_ac97.done);  in s3c_ac97_write()
129 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_write()
131 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_write()
135 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_write()
137 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_write()
139 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))  in s3c_ac97_write()
142 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_write()
144 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);  in s3c_ac97_write()
146 	mutex_unlock(&s3c_ac97.lock);  in s3c_ac97_write()
153 			s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_cold_reset()
156 	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_cold_reset()
164 	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;  in s3c_ac97_warm_reset()
170 	writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_warm_reset()
173 	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_warm_reset()
183 	ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);  in s3c_ac97_irq()
187 		ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_irq()
189 		writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_irq()
191 		complete(&s3c_ac97.done);  in s3c_ac97_irq()
194 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_irq()
196 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_irq()
213 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_trigger()
235 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_trigger()
245 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_mic_trigger()
261 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);  in s3c_ac97_mic_trigger()
345 	s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res);  in s3c_ac97_probe()
346 	if (IS_ERR(s3c_ac97.regs))  in s3c_ac97_probe()
347 		return PTR_ERR(s3c_ac97.regs);  in s3c_ac97_probe()
356 	init_completion(&s3c_ac97.done);  in s3c_ac97_probe()
357 	mutex_init(&s3c_ac97.lock);  in s3c_ac97_probe()
359 	s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97");  in s3c_ac97_probe()
360 	if (IS_ERR(s3c_ac97.ac97_clk)) {  in s3c_ac97_probe()
365 	clk_prepare_enable(s3c_ac97.ac97_clk);  in s3c_ac97_probe()
402 	clk_disable_unprepare(s3c_ac97.ac97_clk);  in s3c_ac97_probe()
416 	clk_disable_unprepare(s3c_ac97.ac97_clk);  in s3c_ac97_remove()