106 	unsigned long val;  in zx_i2s_tx_en()  local
108 	val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_tx_en()
110 		val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;  in zx_i2s_tx_en()
112 		val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);  in zx_i2s_tx_en()
113 	writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_tx_en()
118 	unsigned long val;  in zx_i2s_rx_en()  local
120 	val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_rx_en()
122 		val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;  in zx_i2s_rx_en()
124 		val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);  in zx_i2s_rx_en()
125 	writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_rx_en()
130 	unsigned long val;  in zx_i2s_tx_dma_en()  local
132 	val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);  in zx_i2s_tx_dma_en()
133 	val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);  in zx_i2s_tx_dma_en()
135 		val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;  in zx_i2s_tx_dma_en()
137 		val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;  in zx_i2s_tx_dma_en()
138 	writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);  in zx_i2s_tx_dma_en()
143 	unsigned long val;  in zx_i2s_rx_dma_en()  local
145 	val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);  in zx_i2s_rx_dma_en()
146 	val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);  in zx_i2s_rx_dma_en()
148 		val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;  in zx_i2s_rx_dma_en()
150 		val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;  in zx_i2s_rx_dma_en()
151 	writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);  in zx_i2s_rx_dma_en()
181 	unsigned long val;  in zx_i2s_set_fmt()  local
183 	val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_set_fmt()
184 	val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |  in zx_i2s_set_fmt()
190 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);  in zx_i2s_set_fmt()
193 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);  in zx_i2s_set_fmt()
196 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);  in zx_i2s_set_fmt()
206 		val |= ZX_I2S_TIMING_MAST;  in zx_i2s_set_fmt()
210 		val |= ZX_I2S_TIMING_SLAVE;  in zx_i2s_set_fmt()
217 	writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_set_fmt()
228 	unsigned long val, format;  in zx_i2s_hw_params()  local
234 	val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_hw_params()
235 	val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |  in zx_i2s_hw_params()
256 	val |= ZX_I2S_TIMING_TS_WIDTH(len) | ZX_I2S_TIMING_DATA_SIZE(len);  in zx_i2s_hw_params()
275 	val |= ZX_I2S_TIMING_LANE(lane);  in zx_i2s_hw_params()
276 	val |= ZX_I2S_TIMING_TSCFG(chn_cfg);  in zx_i2s_hw_params()
277 	val |= ZX_I2S_TIMING_CHN(ch_num);  in zx_i2s_hw_params()
278 	writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_hw_params()