1 /* 2 * ni_labpc register definitions. 3 */ 4 5 #ifndef _NI_LABPC_REGS_H 6 #define _NI_LABPC_REGS_H 7 8 /* 9 * Register map (all registers are 8-bit) 10 */ 11 #define STAT1_REG 0x00 /* R: Status 1 reg */ 12 #define STAT1_DAVAIL (1 << 0) 13 #define STAT1_OVERRUN (1 << 1) 14 #define STAT1_OVERFLOW (1 << 2) 15 #define STAT1_CNTINT (1 << 3) 16 #define STAT1_GATA0 (1 << 5) 17 #define STAT1_EXTGATA0 (1 << 6) 18 #define CMD1_REG 0x00 /* W: Command 1 reg */ 19 #define CMD1_MA(x) (((x) & 0x7) << 0) 20 #define CMD1_TWOSCMP (1 << 3) 21 #define CMD1_GAIN(x) (((x) & 0x7) << 4) 22 #define CMD1_SCANEN (1 << 7) 23 #define CMD2_REG 0x01 /* W: Command 2 reg */ 24 #define CMD2_PRETRIG (1 << 0) 25 #define CMD2_HWTRIG (1 << 1) 26 #define CMD2_SWTRIG (1 << 2) 27 #define CMD2_TBSEL (1 << 3) 28 #define CMD2_2SDAC0 (1 << 4) 29 #define CMD2_2SDAC1 (1 << 5) 30 #define CMD2_LDAC(x) (1 << (6 + (x))) 31 #define CMD3_REG 0x02 /* W: Command 3 reg */ 32 #define CMD3_DMAEN (1 << 0) 33 #define CMD3_DIOINTEN (1 << 1) 34 #define CMD3_DMATCINTEN (1 << 2) 35 #define CMD3_CNTINTEN (1 << 3) 36 #define CMD3_ERRINTEN (1 << 4) 37 #define CMD3_FIFOINTEN (1 << 5) 38 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ 39 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ 40 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ 41 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */ 42 #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */ 43 #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ 44 #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ 45 #define CMD6_REG 0x0e /* W: Command 6 reg */ 46 #define CMD6_NRSE (1 << 0) 47 #define CMD6_ADCUNI (1 << 1) 48 #define CMD6_DACUNI(x) (1 << (2 + (x))) 49 #define CMD6_HFINTEN (1 << 5) 50 #define CMD6_DQINTEN (1 << 6) 51 #define CMD6_SCANUP (1 << 7) 52 #define CMD4_REG 0x0f /* W: Command 3 reg */ 53 #define CMD4_INTSCAN (1 << 0) 54 #define CMD4_EOIRCV (1 << 1) 55 #define CMD4_ECLKDRV (1 << 2) 56 #define CMD4_SEDIFF (1 << 3) 57 #define CMD4_ECLKRCV (1 << 4) 58 #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ 59 #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ 60 #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ 61 #define CMD5_REG 0x1c /* W: Command 5 reg */ 62 #define CMD5_WRTPRT (1 << 2) 63 #define CMD5_DITHEREN (1 << 3) 64 #define CMD5_CALDACLD (1 << 4) 65 #define CMD5_SCLK (1 << 5) 66 #define CMD5_SDATA (1 << 6) 67 #define CMD5_EEPROMCS (1 << 7) 68 #define STAT2_REG 0x1d /* R: Status 2 reg */ 69 #define STAT2_PROMOUT (1 << 0) 70 #define STAT2_OUTA1 (1 << 1) 71 #define STAT2_FIFONHF (1 << 2) 72 #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ 73 #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ 74 75 #endif /* _NI_LABPC_REGS_H */ 76