1 /* 2 * comedi/drivers/s626.h 3 * Sensoray s626 Comedi driver, header file 4 * 5 * COMEDI - Linux Control and Measurement Device Interface 6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org> 7 * 8 * Based on Sensoray Model 626 Linux driver Version 0.2 9 * Copyright (C) 2002-2004 Sensoray Co., Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #ifndef S626_H_INCLUDED 23 #define S626_H_INCLUDED 24 25 #define S626_DMABUF_SIZE 4096 /* 4k pages */ 26 27 #define S626_ADC_CHANNELS 16 28 #define S626_DAC_CHANNELS 4 29 #define S626_ENCODER_CHANNELS 6 30 #define S626_DIO_CHANNELS 48 31 #define S626_DIO_BANKS 3 /* Number of DIO groups. */ 32 #define S626_DIO_EXTCHANS 40 /* Number of extended-capability 33 * DIO channels. */ 34 35 #define S626_NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ 36 37 /* PCI bus interface types. */ 38 #define S626_INTEL 1 /* Intel bus type. */ 39 #define S626_MOTOROLA 2 /* Motorola bus type. */ 40 41 #define S626_PLATFORM S626_INTEL /* *** SELECT PLATFORM TYPE *** */ 42 43 #define S626_RANGE_5V 0x10 /* +/-5V range */ 44 #define S626_RANGE_10V 0x00 /* +/-10V range */ 45 46 #define S626_EOPL 0x80 /* End of ADC poll list marker. */ 47 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */ 48 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */ 49 50 /* Error codes that must be visible to this base class. */ 51 #define S626_ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter 52 * value was specified. */ 53 #define S626_ERR_I2C 0x00020000 /* I2C error. */ 54 #define S626_ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for 55 * counter channel. */ 56 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ 57 58 /* 59 * Organization (physical order) and size (in DWORDs) of logical DMA buffers 60 * contained by ANA_DMABUF. 61 */ 62 #define S626_ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, 63 * plus pre/post garbage samples. */ 64 #define S626_DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single 65 * sample. */ 66 67 /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ 68 69 /* Address offsets, in DWORDS, from base of DMA buffer. */ 70 #define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS 71 72 /* Interrupt enable bit in ISR and IER. */ 73 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ 74 #define S626_IRQ_RPS1 0x10000000 75 #define S626_ISR_AFOU 0x00000800 76 /* Audio fifo under/overflow detected. */ 77 78 #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */ 79 #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */ 80 #define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */ 81 #define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */ 82 #define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */ 83 #define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */ 84 85 /* RPS command codes. */ 86 #define S626_RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ 87 #define S626_RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ 88 #define S626_RPS_NOP 0x00000000 /* NOP */ 89 #define S626_RPS_PAUSE 0x20000000 /* PAUSE */ 90 #define S626_RPS_UPLOAD 0x40000000 /* UPLOAD */ 91 #define S626_RPS_JUMP 0x80000000 /* JUMP */ 92 #define S626_RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ 93 #define S626_RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ 94 #define S626_RPS_STOP 0x50000000 /* STOP */ 95 #define S626_RPS_IRQ 0x60000000 /* IRQ */ 96 97 #define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ 98 #define S626_RPS_INVERT 0x04000000 /* Test for negated 99 * semaphores. */ 100 #define S626_RPS_DEBI 0x00000002 /* DEBI done */ 101 102 #define S626_RPS_SIG0 0x00200000 /* RPS semaphore 0 103 * (used by ADC). */ 104 #define S626_RPS_SIG1 0x00400000 /* RPS semaphore 1 105 * (used by DAC). */ 106 #define S626_RPS_SIG2 0x00800000 /* RPS semaphore 2 107 * (not used). */ 108 #define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */ 109 #define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */ 110 111 #define S626_RPS_SIGADC S626_RPS_SIG0 /* Trigger/status for 112 * ADC's RPS program. */ 113 #define S626_RPS_SIGDAC S626_RPS_SIG1 /* Trigger/status for 114 * DAC's RPS program. */ 115 116 /* RPS clock parameters. */ 117 #define S626_RPSCLK_SCALAR 8 /* This is apparent ratio of 118 * PCI/RPS clks (undocumented!!). */ 119 #define S626_RPSCLK_PER_US (33 / S626_RPSCLK_SCALAR) 120 /* Number of RPS clocks in one 121 * microsecond. */ 122 123 /* Event counter source addresses. */ 124 #define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ 125 126 /* GPIO constants. */ 127 #define S626_GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, 128 * GPIO3 = IRQ; GPIO1 = out. */ 129 #define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ 130 #define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ 131 132 /* Primary Status Register (PSR) constants. */ 133 #define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */ 134 #define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */ 135 #define S626_PSR_A2_IN 0x00008000 /* Audio output DMA2 protection 136 * address reached. */ 137 #define S626_PSR_AFOU 0x00000800 /* Audio FIFO under/overflow 138 * detected. */ 139 #define S626_PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 140 * 1=AdcIdle. */ 141 #define S626_PSR_EC0S 0x00000001 /* Event counter 0 threshold 142 * reached. */ 143 144 /* Secondary Status Register (SSR) constants. */ 145 #define S626_SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO 146 * under/overflow detected. */ 147 148 /* Master Control Register 1 (MC1) constants. */ 149 #define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ 150 #define S626_MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled 151 * enables. */ 152 153 #define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ 154 #define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ 155 #define S626_MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */ 156 #define S626_MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */ 157 #define S626_MC1_I2C 0x0100 /* Enab/disable I2C interface. */ 158 #define S626_MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */ 159 #define S626_MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */ 160 #define S626_MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */ 161 162 /* Master Control Register 2 (MC2) constants. */ 163 #define S626_MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ 164 #define S626_MC2_UPLD_IIC 0x0001 /* Upload I2C. */ 165 #define S626_MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ 166 #define S626_MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ 167 #define S626_MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ 168 169 #define S626_MC2_ADC_RPS S626_MC2_RPSSIG0 /* ADC RPS busy. */ 170 #define S626_MC2_DAC_RPS S626_MC2_RPSSIG1 /* DAC RPS busy. */ 171 172 /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ 173 #define S626_P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ 174 #define S626_P_DEBICFG 0x007C /* DEBI configuration. */ 175 #define S626_P_DEBICMD 0x0080 /* DEBI command. */ 176 #define S626_P_DEBIPAGE 0x0084 /* DEBI page. */ 177 #define S626_P_DEBIAD 0x0088 /* DEBI target address. */ 178 #define S626_P_I2CCTRL 0x008C /* I2C control. */ 179 #define S626_P_I2CSTAT 0x0090 /* I2C status. */ 180 #define S626_P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf 181 * address. */ 182 #define S626_P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf 183 * protection address. */ 184 #define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ 185 #define S626_P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf 186 * address. */ 187 #define S626_P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf 188 * protection address. */ 189 #define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ 190 #define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */ 191 #define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */ 192 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ 193 #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ 194 #define S626_P_IER 0x00DC /* Interrupt enable. */ 195 #define S626_P_GPIO 0x00E0 /* General-purpose I/O. */ 196 #define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ 197 #define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */ 198 #define S626_P_ACON1 0x00F4 /* Audio control 1. */ 199 #define S626_P_ACON2 0x00F8 /* Audio control 2. */ 200 #define S626_P_MC1 0x00FC /* Master control 1. */ 201 #define S626_P_MC2 0x0100 /* Master control 2. */ 202 #define S626_P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ 203 #define S626_P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ 204 #define S626_P_ISR 0x010C /* Interrupt status. */ 205 #define S626_P_PSR 0x0110 /* Primary status. */ 206 #define S626_P_SSR 0x0114 /* Secondary status. */ 207 #define S626_P_EC1R 0x0118 /* Event counter set 1. */ 208 #define S626_P_ADP4 0x0138 /* Logical audio DMA pointer of audio 209 * input FIFO A2_IN. */ 210 #define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ 211 #define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ 212 #define S626_P_TSL1 0x0180 /* Audio time slot list 1. */ 213 #define S626_P_TSL2 0x01C0 /* Audio time slot list 2. */ 214 215 /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ 216 /* Analog I/O registers: */ 217 #define S626_LP_DACPOL 0x0082 /* Write DAC polarity. */ 218 #define S626_LP_GSEL 0x0084 /* Write ADC gain. */ 219 #define S626_LP_ISEL 0x0086 /* Write ADC channel select. */ 220 221 /* Digital I/O registers */ 222 #define S626_LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */ 223 #define S626_LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */ 224 #define S626_LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */ 225 #define S626_LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */ 226 #define S626_LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */ 227 #define S626_LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */ 228 #define S626_LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */ 229 #define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ 230 #define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ 231 232 /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */ 233 #define S626_LP_CRA(x) (0x0000 + (((x) % 3) * 0x4)) 234 #define S626_LP_CRB(x) (0x0002 + (((x) % 3) * 0x4)) 235 236 /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */ 237 #define S626_LP_CNTR(x) (0x000c + (((x) < 3) ? 0x0 : 0x4) + \ 238 (((x) % 3) * 0x8)) 239 240 /* Miscellaneous Registers (read/write): */ 241 #define S626_LP_MISC1 0x0088 /* Read/write Misc1. */ 242 #define S626_LP_WRMISC2 0x0090 /* Write Misc2. */ 243 #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */ 244 245 /* Bit masks for MISC1 register that are the same for reads and writes. */ 246 #define S626_MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear 247 * Watchdog bit). */ 248 #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ 249 #define S626_MISC1_EDCAP 0x1000 /* Enable edge capture on DIO chans 250 * specified by S626_LP_WRCAPSELx. */ 251 #define S626_MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified 252 * DIO chans. */ 253 254 /* Bit masks for MISC1 register reads. */ 255 #define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ 256 257 /* Bit masks for MISC2 register writes. */ 258 #define S626_WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ 259 #define S626_WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */ 260 261 /* Bit masks for MISC2 register that are the same for reads and writes. */ 262 #define S626_MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ 263 #define S626_MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ 264 #define S626_MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */ 265 266 /* Bit masks for ACON1 register. */ 267 #define S626_A2_RUN 0x40000000 /* Run A2 based on TSL2. */ 268 #define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */ 269 #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */ 270 #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */ 271 #define S626_WS_MODES 0x00019999 /* WS0 = TSL1 trigger input, 272 * WS1-WS4 = CS* outputs. */ 273 274 #if S626_PLATFORM == S626_INTEL /* Base ACON1 config: always run 275 * A1 based on TSL1. */ 276 #define S626_ACON1_BASE (S626_WS_MODES | S626_A1_RUN) 277 #elif S626_PLATFORM == S626_MOTOROLA 278 #define S626_ACON1_BASE \ 279 (S626_WS_MODES | S626_A1_RUN | S626_A1_SWAP | S626_A2_SWAP) 280 #endif 281 282 #define S626_ACON1_ADCSTART S626_ACON1_BASE /* Start ADC: run A1 283 * based on TSL1. */ 284 #define S626_ACON1_DACSTART (S626_ACON1_BASE | S626_A2_RUN) 285 /* Start transmit to DAC: run A2 based on TSL2. */ 286 #define S626_ACON1_DACSTOP S626_ACON1_BASE /* Halt A2. */ 287 288 /* Bit masks for ACON2 register. */ 289 #define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ 290 #define S626_A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 291 * (DACs). */ 292 #define S626_A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 293 * (DACs). */ 294 #define S626_A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 295 * (DACs). */ 296 #define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ 297 #define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ 298 #define S626_ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 299 * active-low bits. */ 300 301 #define S626_ACON2_INIT (S626_ACON2_XORMASK ^ \ 302 (S626_A1_CLKSRC_BCLK1 | S626_A2_CLKSRC_X2 | \ 303 S626_INVERT_BCLK2 | S626_BCLK2_OE)) 304 305 /* Bit masks for timeslot records. */ 306 #define S626_WS1 0x40000000 /* WS output to assert. */ 307 #define S626_WS2 0x20000000 308 #define S626_WS3 0x10000000 309 #define S626_WS4 0x08000000 310 #define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */ 311 #define S626_SDW_A1 0x00800000 /* Store rcv'd char at next char 312 * slot of DWORD1 buffer. */ 313 #define S626_SIB_A1 0x00400000 /* Store rcv'd char at next 314 * char slot of FB1 buffer. */ 315 #define S626_SF_A1 0x00200000 /* Write unsigned long 316 * buffer to input FIFO. */ 317 318 /* Select parallel-to-serial converter's data source: */ 319 #define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */ 320 #define S626_XFIFO_1 0x00000010 /* Data fifo byte 1. */ 321 #define S626_XFIFO_2 0x00000020 /* Data fifo byte 2. */ 322 #define S626_XFIFO_3 0x00000030 /* Data fifo byte 3. */ 323 #define S626_XFB0 0x00000040 /* FB_BUFFER byte 0. */ 324 #define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */ 325 #define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */ 326 #define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */ 327 #define S626_SIB_A2 0x00000200 /* Store next dword from A2's 328 * input shifter to FB2 329 * buffer. */ 330 #define S626_SF_A2 0x00000100 /* Store next dword from A2's 331 * input shifter to its input 332 * fifo. */ 333 #define S626_LF_A2 0x00000080 /* Load next dword from A2's 334 * output fifo into its 335 * output dword buffer. */ 336 #define S626_XSD2 0x00000008 /* Shift data out on SD2. */ 337 #define S626_RSD3 0x00001800 /* Shift data in on SD3. */ 338 #define S626_RSD2 0x00001000 /* Shift data in on SD2. */ 339 #define S626_LOW_A2 0x00000002 /* Drive last SD low for 7 clks, 340 * then tri-state. */ 341 #define S626_EOS 0x00000001 /* End of superframe. */ 342 343 /* I2C configuration constants. */ 344 #define S626_I2C_CLKSEL 0x0400 /* I2C bit rate = 345 * PCIclk/480 = 68.75 KHz. */ 346 #define S626_I2C_BITRATE 68.75 /* I2C bus data bit rate 347 * (determined by 348 * S626_I2C_CLKSEL) in KHz. */ 349 #define S626_I2C_WRTIME 15.0 /* Worst case time, in msec, 350 * for EEPROM internal write 351 * op. */ 352 353 /* I2C manifest constants. */ 354 355 /* Max retries to wait for EEPROM write. */ 356 #define S626_I2C_RETRIES (S626_I2C_WRTIME * S626_I2C_BITRATE / 9.0) 357 #define S626_I2C_ERR 0x0002 /* I2C control/status flag ERROR. */ 358 #define S626_I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */ 359 #define S626_I2C_ABORT 0x0080 /* I2C status flag ABORT. */ 360 #define S626_I2C_ATTRSTART 0x3 /* I2C attribute START. */ 361 #define S626_I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ 362 #define S626_I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ 363 #define S626_I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ 364 365 /* Code macros used for constructing I2C command bytes. */ 366 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) 367 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) 368 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) 369 370 /* DEBI command constants. */ 371 #define S626_DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is always 372 * 2 bytes. */ 373 #define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */ 374 #define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */ 375 376 /* Read immediate 2 bytes. */ 377 #define S626_DEBI_CMD_RDWORD (S626_DEBI_CMD_READ | S626_DEBI_CMD_SIZE16) 378 379 /* Write immediate 2 bytes. */ 380 #define S626_DEBI_CMD_WRWORD (S626_DEBI_CMD_WRITE | S626_DEBI_CMD_SIZE16) 381 382 /* DEBI configuration constants. */ 383 #define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* Enable external interrupt 384 * on GPIO3. */ 385 #define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */ 386 /* Transfer when XIRQ 387 * deasserted. */ 388 #define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ 389 #define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ 390 391 /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ 392 #define S626_DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after this many 393 * clocks. */ 394 395 /* 2-bit field that specifies Endian byte lane steering: */ 396 #define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't swap any 397 * bytes (Intel). */ 398 #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ 399 #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ 400 #define S626_DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to serve 401 * 16-bit cycles. */ 402 #define S626_DEBI_CFG_INC 0x00040000 /* Enable address increment 403 * for block transfers. */ 404 #define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ 405 #define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ 406 407 #if S626_PLATFORM == S626_INTEL 408 409 #define S626_DEBI_TOUT 7 /* Wait 7 PCI clocks (212 ns) before 410 * polling RDY. */ 411 412 /* Intel byte lane steering (pass through all byte lanes). */ 413 #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_NONE 414 415 #elif S626_PLATFORM == S626_MOTOROLA 416 417 #define S626_DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) maximum 418 * before timing out. */ 419 420 /* Motorola byte lane steering. */ 421 #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_2 422 423 #endif 424 425 /* DEBI page table constants. */ 426 #define S626_DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ 427 428 /* ******* EXTRA FROM OTHER SENSORAY * .h ******* */ 429 430 /* LoadSrc values: */ 431 #define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */ 432 #define S626_LOADSRC_OVER 1 /* Preload core in response to 433 * Overflow. */ 434 #define S626_LOADSRCB_OVERA 2 /* Preload B core in response to 435 * A Overflow. */ 436 #define S626_LOADSRC_NONE 3 /* Never preload core. */ 437 438 /* IntSrc values: */ 439 #define S626_INTSRC_NONE 0 /* Interrupts disabled. */ 440 #define S626_INTSRC_OVER 1 /* Interrupt on Overflow. */ 441 #define S626_INTSRC_INDX 2 /* Interrupt on Index. */ 442 #define S626_INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ 443 444 /* LatchSrc values: */ 445 #define S626_LATCHSRC_AB_READ 0 /* Latch on read. */ 446 #define S626_LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ 447 #define S626_LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ 448 #define S626_LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ 449 450 /* IndxSrc values: */ 451 #define S626_INDXSRC_ENCODER 0 /* Encoder. */ 452 #define S626_INDXSRC_DIGIN 1 /* Digital inputs. */ 453 #define S626_INDXSRC_SOFT 2 /* S/w controlled by IndxPol bit. */ 454 #define S626_INDXSRC_DISABLED 3 /* Index disabled. */ 455 456 /* IndxPol values: */ 457 #define S626_INDXPOL_POS 0 /* Index input is active high. */ 458 #define S626_INDXPOL_NEG 1 /* Index input is active low. */ 459 460 /* Logical encoder mode values: */ 461 #define S626_ENCMODE_COUNTER 0 /* Counter mode. */ 462 #define S626_ENCMODE_TIMER 2 /* Timer mode. */ 463 #define S626_ENCMODE_EXTENDER 3 /* Extender mode. */ 464 465 /* Physical CntSrc values (for Counter A source and Counter B source): */ 466 #define S626_CNTSRC_ENCODER 0 /* Encoder */ 467 #define S626_CNTSRC_DIGIN 1 /* Digital inputs */ 468 #define S626_CNTSRC_SYSCLK 2 /* System clock up */ 469 #define S626_CNTSRC_SYSCLK_DOWN 3 /* System clock down */ 470 471 /* ClkPol values: */ 472 #define S626_CLKPOL_POS 0 /* Counter/Extender clock is 473 * active high. */ 474 #define S626_CLKPOL_NEG 1 /* Counter/Extender clock is 475 * active low. */ 476 #define S626_CNTDIR_UP 0 /* Timer counts up. */ 477 #define S626_CNTDIR_DOWN 1 /* Timer counts down. */ 478 479 /* ClkEnab values: */ 480 #define S626_CLKENAB_ALWAYS 0 /* Clock always enabled. */ 481 #define S626_CLKENAB_INDEX 1 /* Clock is enabled by index. */ 482 483 /* ClkMult values: */ 484 #define S626_CLKMULT_4X 0 /* 4x clock multiplier. */ 485 #define S626_CLKMULT_2X 1 /* 2x clock multiplier. */ 486 #define S626_CLKMULT_1X 2 /* 1x clock multiplier. */ 487 #define S626_CLKMULT_SPECIAL 3 /* Special clock multiplier value. */ 488 489 /* Sanity-check limits for parameters. */ 490 491 #define S626_NUM_COUNTERS 6 /* Maximum valid counter 492 * logical channel number. */ 493 #define S626_NUM_INTSOURCES 4 494 #define S626_NUM_LATCHSOURCES 4 495 #define S626_NUM_CLKMULTS 4 496 #define S626_NUM_CLKSOURCES 4 497 #define S626_NUM_CLKPOLS 2 498 #define S626_NUM_INDEXPOLS 2 499 #define S626_NUM_INDEXSOURCES 2 500 #define S626_NUM_LOADTRIGS 4 501 502 /* General macros for manipulating bitfields: */ 503 #define S626_MAKE(x, w, p) (((x) & ((1 << (w)) - 1)) << (p)) 504 #define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1)) 505 506 /* Bit field positions in CRA: */ 507 #define S626_CRABIT_INDXSRC_B 14 /* B index source. */ 508 #define S626_CRABIT_CNTSRC_B 12 /* B counter source. */ 509 #define S626_CRABIT_INDXPOL_A 11 /* A index polarity. */ 510 #define S626_CRABIT_LOADSRC_A 9 /* A preload trigger. */ 511 #define S626_CRABIT_CLKMULT_A 7 /* A clock multiplier. */ 512 #define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */ 513 #define S626_CRABIT_CLKPOL_A 4 /* A clock polarity. */ 514 #define S626_CRABIT_INDXSRC_A 2 /* A index source. */ 515 #define S626_CRABIT_CNTSRC_A 0 /* A counter source. */ 516 517 /* Bit field widths in CRA: */ 518 #define S626_CRAWID_INDXSRC_B 2 519 #define S626_CRAWID_CNTSRC_B 2 520 #define S626_CRAWID_INDXPOL_A 1 521 #define S626_CRAWID_LOADSRC_A 2 522 #define S626_CRAWID_CLKMULT_A 2 523 #define S626_CRAWID_INTSRC_A 2 524 #define S626_CRAWID_CLKPOL_A 1 525 #define S626_CRAWID_INDXSRC_A 2 526 #define S626_CRAWID_CNTSRC_A 2 527 528 /* Bit field masks for CRA: */ 529 #define S626_CRAMSK_INDXSRC_B S626_SET_CRA_INDXSRC_B(~0) 530 #define S626_CRAMSK_CNTSRC_B S626_SET_CRA_CNTSRC_B(~0) 531 #define S626_CRAMSK_INDXPOL_A S626_SET_CRA_INDXPOL_A(~0) 532 #define S626_CRAMSK_LOADSRC_A S626_SET_CRA_LOADSRC_A(~0) 533 #define S626_CRAMSK_CLKMULT_A S626_SET_CRA_CLKMULT_A(~0) 534 #define S626_CRAMSK_INTSRC_A S626_SET_CRA_INTSRC_A(~0) 535 #define S626_CRAMSK_CLKPOL_A S626_SET_CRA_CLKPOL_A(~0) 536 #define S626_CRAMSK_INDXSRC_A S626_SET_CRA_INDXSRC_A(~0) 537 #define S626_CRAMSK_CNTSRC_A S626_SET_CRA_CNTSRC_A(~0) 538 539 /* Construct parts of the CRA value: */ 540 #define S626_SET_CRA_INDXSRC_B(x) \ 541 S626_MAKE((x), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) 542 #define S626_SET_CRA_CNTSRC_B(x) \ 543 S626_MAKE((x), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) 544 #define S626_SET_CRA_INDXPOL_A(x) \ 545 S626_MAKE((x), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) 546 #define S626_SET_CRA_LOADSRC_A(x) \ 547 S626_MAKE((x), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) 548 #define S626_SET_CRA_CLKMULT_A(x) \ 549 S626_MAKE((x), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) 550 #define S626_SET_CRA_INTSRC_A(x) \ 551 S626_MAKE((x), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) 552 #define S626_SET_CRA_CLKPOL_A(x) \ 553 S626_MAKE((x), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) 554 #define S626_SET_CRA_INDXSRC_A(x) \ 555 S626_MAKE((x), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) 556 #define S626_SET_CRA_CNTSRC_A(x) \ 557 S626_MAKE((x), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) 558 559 /* Extract parts of the CRA value: */ 560 #define S626_GET_CRA_INDXSRC_B(v) \ 561 S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) 562 #define S626_GET_CRA_CNTSRC_B(v) \ 563 S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) 564 #define S626_GET_CRA_INDXPOL_A(v) \ 565 S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) 566 #define S626_GET_CRA_LOADSRC_A(v) \ 567 S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) 568 #define S626_GET_CRA_CLKMULT_A(v) \ 569 S626_UNMAKE((v), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) 570 #define S626_GET_CRA_INTSRC_A(v) \ 571 S626_UNMAKE((v), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) 572 #define S626_GET_CRA_CLKPOL_A(v) \ 573 S626_UNMAKE((v), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) 574 #define S626_GET_CRA_INDXSRC_A(v) \ 575 S626_UNMAKE((v), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) 576 #define S626_GET_CRA_CNTSRC_A(v) \ 577 S626_UNMAKE((v), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) 578 579 /* Bit field positions in CRB: */ 580 #define S626_CRBBIT_INTRESETCMD 15 /* (w) Interrupt reset command. */ 581 #define S626_CRBBIT_CNTDIR_B 15 /* (r) B counter direction. */ 582 #define S626_CRBBIT_INTRESET_B 14 /* (w) B interrupt reset enable. */ 583 #define S626_CRBBIT_OVERDO_A 14 /* (r) A overflow routed to dig. out. */ 584 #define S626_CRBBIT_INTRESET_A 13 /* (w) A interrupt reset enable. */ 585 #define S626_CRBBIT_OVERDO_B 13 /* (r) B overflow routed to dig. out. */ 586 #define S626_CRBBIT_CLKENAB_A 12 /* A clock enable. */ 587 #define S626_CRBBIT_INTSRC_B 10 /* B interrupt source. */ 588 #define S626_CRBBIT_LATCHSRC 8 /* A/B latch source. */ 589 #define S626_CRBBIT_LOADSRC_B 6 /* B preload trigger. */ 590 #define S626_CRBBIT_CLEAR_B 7 /* B cleared when A overflows. */ 591 #define S626_CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ 592 #define S626_CRBBIT_CLKENAB_B 2 /* B clock enable. */ 593 #define S626_CRBBIT_INDXPOL_B 1 /* B index polarity. */ 594 #define S626_CRBBIT_CLKPOL_B 0 /* B clock polarity. */ 595 596 /* Bit field widths in CRB: */ 597 #define S626_CRBWID_INTRESETCMD 1 598 #define S626_CRBWID_CNTDIR_B 1 599 #define S626_CRBWID_INTRESET_B 1 600 #define S626_CRBWID_OVERDO_A 1 601 #define S626_CRBWID_INTRESET_A 1 602 #define S626_CRBWID_OVERDO_B 1 603 #define S626_CRBWID_CLKENAB_A 1 604 #define S626_CRBWID_INTSRC_B 2 605 #define S626_CRBWID_LATCHSRC 2 606 #define S626_CRBWID_LOADSRC_B 2 607 #define S626_CRBWID_CLEAR_B 1 608 #define S626_CRBWID_CLKMULT_B 2 609 #define S626_CRBWID_CLKENAB_B 1 610 #define S626_CRBWID_INDXPOL_B 1 611 #define S626_CRBWID_CLKPOL_B 1 612 613 /* Bit field masks for CRB: */ 614 #define S626_CRBMSK_INTRESETCMD S626_SET_CRB_INTRESETCMD(~0) /* (w) */ 615 #define S626_CRBMSK_CNTDIR_B S626_CRBMSK_INTRESETCMD /* (r) */ 616 #define S626_CRBMSK_INTRESET_B S626_SET_CRB_INTRESET_B(~0) /* (w) */ 617 #define S626_CRBMSK_OVERDO_A S626_CRBMSK_INTRESET_B /* (r) */ 618 #define S626_CRBMSK_INTRESET_A S626_SET_CRB_INTRESET_A(~0) /* (w) */ 619 #define S626_CRBMSK_OVERDO_B S626_CRBMSK_INTRESET_A /* (r) */ 620 #define S626_CRBMSK_CLKENAB_A S626_SET_CRB_CLKENAB_A(~0) 621 #define S626_CRBMSK_INTSRC_B S626_SET_CRB_INTSRC_B(~0) 622 #define S626_CRBMSK_LATCHSRC S626_SET_CRB_LATCHSRC(~0) 623 #define S626_CRBMSK_LOADSRC_B S626_SET_CRB_LOADSRC_B(~0) 624 #define S626_CRBMSK_CLEAR_B S626_SET_CRB_CLEAR_B(~0) 625 #define S626_CRBMSK_CLKMULT_B S626_SET_CRB_CLKMULT_B(~0) 626 #define S626_CRBMSK_CLKENAB_B S626_SET_CRB_CLKENAB_B(~0) 627 #define S626_CRBMSK_INDXPOL_B S626_SET_CRB_INDXPOL_B(~0) 628 #define S626_CRBMSK_CLKPOL_B S626_SET_CRB_CLKPOL_B(~0) 629 630 /* Interrupt reset control bits. */ 631 #define S626_CRBMSK_INTCTRL (S626_CRBMSK_INTRESETCMD | \ 632 S626_CRBMSK_INTRESET_A | \ 633 S626_CRBMSK_INTRESET_B) 634 635 /* Construct parts of the CRB value: */ 636 #define S626_SET_CRB_INTRESETCMD(x) \ 637 S626_MAKE((x), S626_CRBWID_INTRESETCMD, S626_CRBBIT_INTRESETCMD) 638 #define S626_SET_CRB_INTRESET_B(x) \ 639 S626_MAKE((x), S626_CRBWID_INTRESET_B, S626_CRBBIT_INTRESET_B) 640 #define S626_SET_CRB_INTRESET_A(x) \ 641 S626_MAKE((x), S626_CRBWID_INTRESET_A, S626_CRBBIT_INTRESET_A) 642 #define S626_SET_CRB_CLKENAB_A(x) \ 643 S626_MAKE((x), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) 644 #define S626_SET_CRB_INTSRC_B(x) \ 645 S626_MAKE((x), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) 646 #define S626_SET_CRB_LATCHSRC(x) \ 647 S626_MAKE((x), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) 648 #define S626_SET_CRB_LOADSRC_B(x) \ 649 S626_MAKE((x), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) 650 #define S626_SET_CRB_CLEAR_B(x) \ 651 S626_MAKE((x), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) 652 #define S626_SET_CRB_CLKMULT_B(x) \ 653 S626_MAKE((x), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) 654 #define S626_SET_CRB_CLKENAB_B(x) \ 655 S626_MAKE((x), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) 656 #define S626_SET_CRB_INDXPOL_B(x) \ 657 S626_MAKE((x), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) 658 #define S626_SET_CRB_CLKPOL_B(x) \ 659 S626_MAKE((x), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) 660 661 /* Extract parts of the CRB value: */ 662 #define S626_GET_CRB_CNTDIR_B(v) \ 663 S626_UNMAKE((v), S626_CRBWID_CNTDIR_B, S626_CRBBIT_CNTDIR_B) 664 #define S626_GET_CRB_OVERDO_A(v) \ 665 S626_UNMAKE((v), S626_CRBWID_OVERDO_A, S626_CRBBIT_OVERDO_A) 666 #define S626_GET_CRB_OVERDO_B(v) \ 667 S626_UNMAKE((v), S626_CRBWID_OVERDO_B, S626_CRBBIT_OVERDO_B) 668 #define S626_GET_CRB_CLKENAB_A(v) \ 669 S626_UNMAKE((v), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) 670 #define S626_GET_CRB_INTSRC_B(v) \ 671 S626_UNMAKE((v), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) 672 #define S626_GET_CRB_LATCHSRC(v) \ 673 S626_UNMAKE((v), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) 674 #define S626_GET_CRB_LOADSRC_B(v) \ 675 S626_UNMAKE((v), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) 676 #define S626_GET_CRB_CLEAR_B(v) \ 677 S626_UNMAKE((v), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) 678 #define S626_GET_CRB_CLKMULT_B(v) \ 679 S626_UNMAKE((v), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) 680 #define S626_GET_CRB_CLKENAB_B(v) \ 681 S626_UNMAKE((v), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) 682 #define S626_GET_CRB_INDXPOL_B(v) \ 683 S626_UNMAKE((v), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) 684 #define S626_GET_CRB_CLKPOL_B(v) \ 685 S626_UNMAKE((v), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) 686 687 /* Bit field positions for standardized SETUP structure: */ 688 #define S626_STDBIT_INTSRC 13 689 #define S626_STDBIT_LATCHSRC 11 690 #define S626_STDBIT_LOADSRC 9 691 #define S626_STDBIT_INDXSRC 7 692 #define S626_STDBIT_INDXPOL 6 693 #define S626_STDBIT_ENCMODE 4 694 #define S626_STDBIT_CLKPOL 3 695 #define S626_STDBIT_CLKMULT 1 696 #define S626_STDBIT_CLKENAB 0 697 698 /* Bit field widths for standardized SETUP structure: */ 699 #define S626_STDWID_INTSRC 2 700 #define S626_STDWID_LATCHSRC 2 701 #define S626_STDWID_LOADSRC 2 702 #define S626_STDWID_INDXSRC 2 703 #define S626_STDWID_INDXPOL 1 704 #define S626_STDWID_ENCMODE 2 705 #define S626_STDWID_CLKPOL 1 706 #define S626_STDWID_CLKMULT 2 707 #define S626_STDWID_CLKENAB 1 708 709 /* Bit field masks for standardized SETUP structure: */ 710 #define S626_STDMSK_INTSRC S626_SET_STD_INTSRC(~0) 711 #define S626_STDMSK_LATCHSRC S626_SET_STD_LATCHSRC(~0) 712 #define S626_STDMSK_LOADSRC S626_SET_STD_LOADSRC(~0) 713 #define S626_STDMSK_INDXSRC S626_SET_STD_INDXSRC(~0) 714 #define S626_STDMSK_INDXPOL S626_SET_STD_INDXPOL(~0) 715 #define S626_STDMSK_ENCMODE S626_SET_STD_ENCMODE(~0) 716 #define S626_STDMSK_CLKPOL S626_SET_STD_CLKPOL(~0) 717 #define S626_STDMSK_CLKMULT S626_SET_STD_CLKMULT(~0) 718 #define S626_STDMSK_CLKENAB S626_SET_STD_CLKENAB(~0) 719 720 /* Construct parts of standardized SETUP structure: */ 721 #define S626_SET_STD_INTSRC(x) \ 722 S626_MAKE((x), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) 723 #define S626_SET_STD_LATCHSRC(x) \ 724 S626_MAKE((x), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) 725 #define S626_SET_STD_LOADSRC(x) \ 726 S626_MAKE((x), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) 727 #define S626_SET_STD_INDXSRC(x) \ 728 S626_MAKE((x), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) 729 #define S626_SET_STD_INDXPOL(x) \ 730 S626_MAKE((x), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) 731 #define S626_SET_STD_ENCMODE(x) \ 732 S626_MAKE((x), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) 733 #define S626_SET_STD_CLKPOL(x) \ 734 S626_MAKE((x), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) 735 #define S626_SET_STD_CLKMULT(x) \ 736 S626_MAKE((x), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) 737 #define S626_SET_STD_CLKENAB(x) \ 738 S626_MAKE((x), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) 739 740 /* Extract parts of standardized SETUP structure: */ 741 #define S626_GET_STD_INTSRC(v) \ 742 S626_UNMAKE((v), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) 743 #define S626_GET_STD_LATCHSRC(v) \ 744 S626_UNMAKE((v), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) 745 #define S626_GET_STD_LOADSRC(v) \ 746 S626_UNMAKE((v), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) 747 #define S626_GET_STD_INDXSRC(v) \ 748 S626_UNMAKE((v), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) 749 #define S626_GET_STD_INDXPOL(v) \ 750 S626_UNMAKE((v), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) 751 #define S626_GET_STD_ENCMODE(v) \ 752 S626_UNMAKE((v), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) 753 #define S626_GET_STD_CLKPOL(v) \ 754 S626_UNMAKE((v), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) 755 #define S626_GET_STD_CLKMULT(v) \ 756 S626_UNMAKE((v), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) 757 #define S626_GET_STD_CLKENAB(v) \ 758 S626_UNMAKE((v), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) 759 760 #endif 761