1 /* 2 * Copyright (C) 2007 Google, Inc. 3 * Author: Brian Swetland <swetland@google.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__ 17 #define __LINUX_USB_GADGET_MSM72K_UDC_H__ 18 19 /* USB phy selector - in TCSR address range */ 20 #define USB2_PHY_SEL 0xfd4ab000 21 22 #define USB_AHBBURST (MSM_USB_BASE + 0x0090) 23 #define USB_AHBMODE (MSM_USB_BASE + 0x0098) 24 #define USB_GENCONFIG_2 (MSM_USB_BASE + 0x00a0) 25 26 #define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ 27 28 #define USB_USBCMD (MSM_USB_BASE + 0x0140) 29 #define USB_PORTSC (MSM_USB_BASE + 0x0184) 30 #define USB_OTGSC (MSM_USB_BASE + 0x01A4) 31 #define USB_USBMODE (MSM_USB_BASE + 0x01A8) 32 #define USB_PHY_CTRL (MSM_USB_BASE + 0x0240) 33 #define USB_PHY_CTRL2 (MSM_USB_BASE + 0x0278) 34 35 #define GENCONFIG_2_SESS_VLD_CTRL_EN BIT(7) 36 #define USBCMD_SESS_VLD_CTRL BIT(25) 37 38 #define USBCMD_RESET 2 39 #define USB_USBINTR (MSM_USB_BASE + 0x0148) 40 41 #define PORTSC_PHCD (1 << 23) /* phy suspend mode */ 42 #define PORTSC_PTS_MASK (3 << 30) 43 #define PORTSC_PTS_ULPI (2 << 30) 44 #define PORTSC_PTS_SERIAL (3 << 30) 45 46 #define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170) 47 #define ULPI_RUN (1 << 30) 48 #define ULPI_WRITE (1 << 29) 49 #define ULPI_READ (0 << 29) 50 #define ULPI_ADDR(n) (((n) & 255) << 16) 51 #define ULPI_DATA(n) ((n) & 255) 52 #define ULPI_DATA_READ(n) (((n) >> 8) & 255) 53 54 /* synopsys 28nm phy registers */ 55 #define ULPI_PWR_CLK_MNG_REG 0x88 56 #define OTG_COMP_DISABLE BIT(0) 57 58 #define ULPI_MISC_A 0x96 59 #define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) 60 #define ULPI_MISC_A_VBUSVLDEXT BIT(0) 61 62 #define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */ 63 #define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */ 64 #define PHY_RETEN (1 << 1) /* PHY retention enable/disable */ 65 #define PHY_POR_ASSERT (1 << 0) /* USB2 28nm PHY POR ASSERT */ 66 67 /* OTG definitions */ 68 #define OTGSC_INTSTS_MASK (0x7f << 16) 69 #define OTGSC_ID (1 << 8) 70 #define OTGSC_BSV (1 << 11) 71 #define OTGSC_IDIS (1 << 16) 72 #define OTGSC_BSVIS (1 << 19) 73 #define OTGSC_IDIE (1 << 24) 74 #define OTGSC_BSVIE (1 << 27) 75 76 #endif /* __LINUX_USB_GADGET_MSM72K_UDC_H__ */ 77