1 /*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/highmem.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spi/spi.h>
23 #include <linux/gpio.h>
24
25 #include "spi-dw.h"
26
27 #ifdef CONFIG_DEBUG_FS
28 #include <linux/debugfs.h>
29 #endif
30
31 /* Slave spi_dev related */
32 struct chip_data {
33 u8 cs; /* chip select pin */
34 u8 tmode; /* TR/TO/RO/EEPROM */
35 u8 type; /* SPI/SSP/MicroWire */
36
37 u8 poll_mode; /* 1 means use poll mode */
38
39 u8 enable_dma;
40 u16 clk_div; /* baud rate divider */
41 u32 speed_hz; /* baud rate */
42 void (*cs_control)(u32 command);
43 };
44
45 #ifdef CONFIG_DEBUG_FS
46 #define SPI_REGS_BUFSIZE 1024
dw_spi_show_regs(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)47 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos)
49 {
50 struct dw_spi *dws = file->private_data;
51 char *buf;
52 u32 len = 0;
53 ssize_t ret;
54
55 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
56 if (!buf)
57 return 0;
58
59 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
60 "%s registers:\n", dev_name(&dws->master->dev));
61 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
62 "=================================\n");
63 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
64 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
65 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
66 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
67 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
69 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
70 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
71 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
72 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
73 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
74 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
75 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
76 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
77 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
78 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
79 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
80 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "=================================\n");
95
96 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
97 kfree(buf);
98 return ret;
99 }
100
101 static const struct file_operations dw_spi_regs_ops = {
102 .owner = THIS_MODULE,
103 .open = simple_open,
104 .read = dw_spi_show_regs,
105 .llseek = default_llseek,
106 };
107
dw_spi_debugfs_init(struct dw_spi * dws)108 static int dw_spi_debugfs_init(struct dw_spi *dws)
109 {
110 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
111 if (!dws->debugfs)
112 return -ENOMEM;
113
114 debugfs_create_file("registers", S_IFREG | S_IRUGO,
115 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
116 return 0;
117 }
118
dw_spi_debugfs_remove(struct dw_spi * dws)119 static void dw_spi_debugfs_remove(struct dw_spi *dws)
120 {
121 debugfs_remove_recursive(dws->debugfs);
122 }
123
124 #else
dw_spi_debugfs_init(struct dw_spi * dws)125 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
126 {
127 return 0;
128 }
129
dw_spi_debugfs_remove(struct dw_spi * dws)130 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
131 {
132 }
133 #endif /* CONFIG_DEBUG_FS */
134
dw_spi_set_cs(struct spi_device * spi,bool enable)135 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
136 {
137 struct dw_spi *dws = spi_master_get_devdata(spi->master);
138 struct chip_data *chip = spi_get_ctldata(spi);
139
140 /* Chip select logic is inverted from spi_set_cs() */
141 if (chip && chip->cs_control)
142 chip->cs_control(!enable);
143
144 if (!enable)
145 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
146 }
147
148 /* Return the max entries we can fill into tx fifo */
tx_max(struct dw_spi * dws)149 static inline u32 tx_max(struct dw_spi *dws)
150 {
151 u32 tx_left, tx_room, rxtx_gap;
152
153 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
154 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
155
156 /*
157 * Another concern is about the tx/rx mismatch, we
158 * though to use (dws->fifo_len - rxflr - txflr) as
159 * one maximum value for tx, but it doesn't cover the
160 * data which is out of tx/rx fifo and inside the
161 * shift registers. So a control from sw point of
162 * view is taken.
163 */
164 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
165 / dws->n_bytes;
166
167 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
168 }
169
170 /* Return the max entries we should read out of rx fifo */
rx_max(struct dw_spi * dws)171 static inline u32 rx_max(struct dw_spi *dws)
172 {
173 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
174
175 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
176 }
177
dw_writer(struct dw_spi * dws)178 static void dw_writer(struct dw_spi *dws)
179 {
180 u32 max = tx_max(dws);
181 u16 txw = 0;
182
183 while (max--) {
184 /* Set the tx word if the transfer's original "tx" is not null */
185 if (dws->tx_end - dws->len) {
186 if (dws->n_bytes == 1)
187 txw = *(u8 *)(dws->tx);
188 else
189 txw = *(u16 *)(dws->tx);
190 }
191 dw_write_io_reg(dws, DW_SPI_DR, txw);
192 dws->tx += dws->n_bytes;
193 }
194 }
195
dw_reader(struct dw_spi * dws)196 static void dw_reader(struct dw_spi *dws)
197 {
198 u32 max = rx_max(dws);
199 u16 rxw;
200
201 while (max--) {
202 rxw = dw_read_io_reg(dws, DW_SPI_DR);
203 /* Care rx only if the transfer's original "rx" is not null */
204 if (dws->rx_end - dws->len) {
205 if (dws->n_bytes == 1)
206 *(u8 *)(dws->rx) = rxw;
207 else
208 *(u16 *)(dws->rx) = rxw;
209 }
210 dws->rx += dws->n_bytes;
211 }
212 }
213
int_error_stop(struct dw_spi * dws,const char * msg)214 static void int_error_stop(struct dw_spi *dws, const char *msg)
215 {
216 spi_reset_chip(dws);
217
218 dev_err(&dws->master->dev, "%s\n", msg);
219 dws->master->cur_msg->status = -EIO;
220 spi_finalize_current_transfer(dws->master);
221 }
222
interrupt_transfer(struct dw_spi * dws)223 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
224 {
225 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
226
227 /* Error handling */
228 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
229 dw_readl(dws, DW_SPI_ICR);
230 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
231 return IRQ_HANDLED;
232 }
233
234 dw_reader(dws);
235 if (dws->rx_end == dws->rx) {
236 spi_mask_intr(dws, SPI_INT_TXEI);
237 spi_finalize_current_transfer(dws->master);
238 return IRQ_HANDLED;
239 }
240 if (irq_status & SPI_INT_TXEI) {
241 spi_mask_intr(dws, SPI_INT_TXEI);
242 dw_writer(dws);
243 /* Enable TX irq always, it will be disabled when RX finished */
244 spi_umask_intr(dws, SPI_INT_TXEI);
245 }
246
247 return IRQ_HANDLED;
248 }
249
dw_spi_irq(int irq,void * dev_id)250 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
251 {
252 struct spi_master *master = dev_id;
253 struct dw_spi *dws = spi_master_get_devdata(master);
254 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
255
256 if (!irq_status)
257 return IRQ_NONE;
258
259 if (!master->cur_msg) {
260 spi_mask_intr(dws, SPI_INT_TXEI);
261 return IRQ_HANDLED;
262 }
263
264 return dws->transfer_handler(dws);
265 }
266
267 /* Must be called inside pump_transfers() */
poll_transfer(struct dw_spi * dws)268 static int poll_transfer(struct dw_spi *dws)
269 {
270 do {
271 dw_writer(dws);
272 dw_reader(dws);
273 cpu_relax();
274 } while (dws->rx_end > dws->rx);
275
276 return 0;
277 }
278
dw_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * transfer)279 static int dw_spi_transfer_one(struct spi_master *master,
280 struct spi_device *spi, struct spi_transfer *transfer)
281 {
282 struct dw_spi *dws = spi_master_get_devdata(master);
283 struct chip_data *chip = spi_get_ctldata(spi);
284 u8 imask = 0;
285 u16 txlevel = 0;
286 u16 clk_div;
287 u32 cr0;
288 int ret;
289
290 dws->dma_mapped = 0;
291
292 dws->tx = (void *)transfer->tx_buf;
293 dws->tx_end = dws->tx + transfer->len;
294 dws->rx = transfer->rx_buf;
295 dws->rx_end = dws->rx + transfer->len;
296 dws->len = transfer->len;
297
298 spi_enable_chip(dws, 0);
299
300 /* Handle per transfer options for bpw and speed */
301 if (transfer->speed_hz != chip->speed_hz) {
302 /* clk_div doesn't support odd number */
303 clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
304
305 chip->speed_hz = transfer->speed_hz;
306 chip->clk_div = clk_div;
307
308 spi_set_clk(dws, chip->clk_div);
309 }
310 if (transfer->bits_per_word == 8) {
311 dws->n_bytes = 1;
312 dws->dma_width = 1;
313 } else if (transfer->bits_per_word == 16) {
314 dws->n_bytes = 2;
315 dws->dma_width = 2;
316 } else {
317 return -EINVAL;
318 }
319 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
320 cr0 = (transfer->bits_per_word - 1)
321 | (chip->type << SPI_FRF_OFFSET)
322 | (spi->mode << SPI_MODE_OFFSET)
323 | (chip->tmode << SPI_TMOD_OFFSET);
324
325 /*
326 * Adjust transfer mode if necessary. Requires platform dependent
327 * chipselect mechanism.
328 */
329 if (chip->cs_control) {
330 if (dws->rx && dws->tx)
331 chip->tmode = SPI_TMOD_TR;
332 else if (dws->rx)
333 chip->tmode = SPI_TMOD_RO;
334 else
335 chip->tmode = SPI_TMOD_TO;
336
337 cr0 &= ~SPI_TMOD_MASK;
338 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
339 }
340
341 dw_writel(dws, DW_SPI_CTRL0, cr0);
342
343 /* Check if current transfer is a DMA transaction */
344 if (master->can_dma && master->can_dma(master, spi, transfer))
345 dws->dma_mapped = master->cur_msg_mapped;
346
347 /* For poll mode just disable all interrupts */
348 spi_mask_intr(dws, 0xff);
349
350 /*
351 * Interrupt mode
352 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
353 */
354 if (dws->dma_mapped) {
355 ret = dws->dma_ops->dma_setup(dws, transfer);
356 if (ret < 0) {
357 spi_enable_chip(dws, 1);
358 return ret;
359 }
360 } else if (!chip->poll_mode) {
361 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
362 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
363
364 /* Set the interrupt mask */
365 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
366 SPI_INT_RXUI | SPI_INT_RXOI;
367 spi_umask_intr(dws, imask);
368
369 dws->transfer_handler = interrupt_transfer;
370 }
371
372 spi_enable_chip(dws, 1);
373
374 if (dws->dma_mapped) {
375 ret = dws->dma_ops->dma_transfer(dws, transfer);
376 if (ret < 0)
377 return ret;
378 }
379
380 if (chip->poll_mode)
381 return poll_transfer(dws);
382
383 return 1;
384 }
385
dw_spi_handle_err(struct spi_master * master,struct spi_message * msg)386 static void dw_spi_handle_err(struct spi_master *master,
387 struct spi_message *msg)
388 {
389 struct dw_spi *dws = spi_master_get_devdata(master);
390
391 if (dws->dma_mapped)
392 dws->dma_ops->dma_stop(dws);
393
394 spi_reset_chip(dws);
395 }
396
397 /* This may be called twice for each spi dev */
dw_spi_setup(struct spi_device * spi)398 static int dw_spi_setup(struct spi_device *spi)
399 {
400 struct dw_spi_chip *chip_info = NULL;
401 struct chip_data *chip;
402 int ret;
403
404 /* Only alloc on first setup */
405 chip = spi_get_ctldata(spi);
406 if (!chip) {
407 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
408 if (!chip)
409 return -ENOMEM;
410 spi_set_ctldata(spi, chip);
411 }
412
413 /*
414 * Protocol drivers may change the chip settings, so...
415 * if chip_info exists, use it
416 */
417 chip_info = spi->controller_data;
418
419 /* chip_info doesn't always exist */
420 if (chip_info) {
421 if (chip_info->cs_control)
422 chip->cs_control = chip_info->cs_control;
423
424 chip->poll_mode = chip_info->poll_mode;
425 chip->type = chip_info->type;
426 }
427
428 chip->tmode = 0; /* Tx & Rx */
429
430 if (gpio_is_valid(spi->cs_gpio)) {
431 ret = gpio_direction_output(spi->cs_gpio,
432 !(spi->mode & SPI_CS_HIGH));
433 if (ret)
434 return ret;
435 }
436
437 return 0;
438 }
439
dw_spi_cleanup(struct spi_device * spi)440 static void dw_spi_cleanup(struct spi_device *spi)
441 {
442 struct chip_data *chip = spi_get_ctldata(spi);
443
444 kfree(chip);
445 spi_set_ctldata(spi, NULL);
446 }
447
448 /* Restart the controller, disable all interrupts, clean rx fifo */
spi_hw_init(struct device * dev,struct dw_spi * dws)449 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
450 {
451 spi_reset_chip(dws);
452
453 /*
454 * Try to detect the FIFO depth if not set by interface driver,
455 * the depth could be from 2 to 256 from HW spec
456 */
457 if (!dws->fifo_len) {
458 u32 fifo;
459
460 for (fifo = 1; fifo < 256; fifo++) {
461 dw_writel(dws, DW_SPI_TXFLTR, fifo);
462 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
463 break;
464 }
465 dw_writel(dws, DW_SPI_TXFLTR, 0);
466
467 dws->fifo_len = (fifo == 1) ? 0 : fifo;
468 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
469 }
470 }
471
dw_spi_add_host(struct device * dev,struct dw_spi * dws)472 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
473 {
474 struct spi_master *master;
475 int ret;
476
477 BUG_ON(dws == NULL);
478
479 master = spi_alloc_master(dev, 0);
480 if (!master)
481 return -ENOMEM;
482
483 dws->master = master;
484 dws->type = SSI_MOTO_SPI;
485 dws->dma_inited = 0;
486 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
487 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
488
489 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master);
490 if (ret < 0) {
491 dev_err(dev, "can not get IRQ\n");
492 goto err_free_master;
493 }
494
495 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
496 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
497 master->bus_num = dws->bus_num;
498 master->num_chipselect = dws->num_cs;
499 master->setup = dw_spi_setup;
500 master->cleanup = dw_spi_cleanup;
501 master->set_cs = dw_spi_set_cs;
502 master->transfer_one = dw_spi_transfer_one;
503 master->handle_err = dw_spi_handle_err;
504 master->max_speed_hz = dws->max_freq;
505 master->dev.of_node = dev->of_node;
506
507 /* Basic HW init */
508 spi_hw_init(dev, dws);
509
510 if (dws->dma_ops && dws->dma_ops->dma_init) {
511 ret = dws->dma_ops->dma_init(dws);
512 if (ret) {
513 dev_warn(dev, "DMA init failed\n");
514 dws->dma_inited = 0;
515 } else {
516 master->can_dma = dws->dma_ops->can_dma;
517 }
518 }
519
520 spi_master_set_devdata(master, dws);
521 ret = devm_spi_register_master(dev, master);
522 if (ret) {
523 dev_err(&master->dev, "problem registering spi master\n");
524 goto err_dma_exit;
525 }
526
527 dw_spi_debugfs_init(dws);
528 return 0;
529
530 err_dma_exit:
531 if (dws->dma_ops && dws->dma_ops->dma_exit)
532 dws->dma_ops->dma_exit(dws);
533 spi_enable_chip(dws, 0);
534 free_irq(dws->irq, master);
535 err_free_master:
536 spi_master_put(master);
537 return ret;
538 }
539 EXPORT_SYMBOL_GPL(dw_spi_add_host);
540
dw_spi_remove_host(struct dw_spi * dws)541 void dw_spi_remove_host(struct dw_spi *dws)
542 {
543 dw_spi_debugfs_remove(dws);
544
545 if (dws->dma_ops && dws->dma_ops->dma_exit)
546 dws->dma_ops->dma_exit(dws);
547
548 spi_shutdown_chip(dws);
549
550 free_irq(dws->irq, dws->master);
551 }
552 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
553
dw_spi_suspend_host(struct dw_spi * dws)554 int dw_spi_suspend_host(struct dw_spi *dws)
555 {
556 int ret;
557
558 ret = spi_master_suspend(dws->master);
559 if (ret)
560 return ret;
561
562 spi_shutdown_chip(dws);
563 return 0;
564 }
565 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
566
dw_spi_resume_host(struct dw_spi * dws)567 int dw_spi_resume_host(struct dw_spi *dws)
568 {
569 int ret;
570
571 spi_hw_init(&dws->master->dev, dws);
572 ret = spi_master_resume(dws->master);
573 if (ret)
574 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
575 return ret;
576 }
577 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
578
579 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
580 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
581 MODULE_LICENSE("GPL v2");
582